This application note describes how to use Renesas SLG59H1401C and SLG59H1403C in PowerMUX and OR'ing applications. Corresponding oscilloscope captures of operational behavior are included

There are a variety of applications where signals from different sources (for example, sensors) are sensed with one ADC. Such systems require an analog multiplexer with analog filters for each channel, because each signal source may have its own set of filter requirements (for example, different cutoff frequencies). An alternative space-efficient and cost-efficient solution is to use one tunable analog filter for all channels. The SLG47004 IC solves this task perfectly.

Tamper detection is a function widely used within critical infrastructure systems such as power meters, water meters, security and fire panels, and any other products where a trigger input needs to be detected and the event recorded in non-volatile memory (Flash memory). The SLG46811 GreenPAK mixed-signal IC is ideally suited for this tamper-detection role when paired with the AT45DB161E Flash memory for recording the event.

This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (ΔΣ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) Converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.

The SAE-J2716 standard is a product of the Data Communications Standards Committee under the Electrical Systems Group of the Motor Vehicle Council. This is the same committee that has produced standards for the widely adopted SAE-J1850, CAN, and LIN protocols. This application report provides an example of how the TMS570 NHET v2 may be used to implement a decoder for the SAE-J2716 (Feb 2008) protocol standard; the decoder presents the data and eliminates the need for CPU to do it. (Note that the standard has been updated again in Jan 2010 but not covered by this application note).

The enhanced DMA (EDMA) controller of the TMS320C64x™ device is a highly efficient data transfer engine. To maximize bandwidth, minimize transfer interference, and fully utilize the resources of the EDMA, it is crucial to understand the architecture of the engine. Transfer requests (TRs) originate from many requestors, including sixty-four programmable EDMA channels, the level 2 (L2) memory controller, and other master peripherals. The EDMA controls access to resources and arbitrates between concurrent transfers. Understanding the interaction points for transfer requests in the EDMA architecture is crucial to creating a system that takes full advantage of EDMA’s capabilities.