This document describes the functionality of the TMS320DM647/DM648 ROM bootloader software. The ROM bootloader resides in the ROM of the device beginning at ROM address 0x00100000. The ROM boot loader (RBL) implements methods for booting in the listed modes. It reads the contents of the BOOTCFG register to determine boot mode and performs appropriate commands to effect boot of device. If an improp
Exactly how inaccurate will a change in temperature make an analog-to-digital or digital-to-analog converter? As designers are well aware, a 12-bit device may provide a much lower accuracy at its oper
Clamping amplifiers limit signal magnitude to protect following circuitry from input overload. The clamping amplifier shown here produces limit levels that track the power supply levels selected in an
This application report compares two approaches for synchronous bus-system designs. The focus of the report is the comparison of a system using central-synchronous system clock (CSSC) with a system operated with a source-synchronous system clock (SSSC).The basic characteristics of lines key factors that influence the bus line delay and the impedance of bus lines are described.The theoretical
Not all low dropout (LDO) linear regulator data sheets provide the voltage dropout information needed for all applications. This application report shows a designer how to use an LDO data sheet's specified dropout performance to determine the dropout voltage at other operating conditions.
The purpose of this application report is to facilitate the migration of MSP430F167/F168/F169/F1610/F1611/F1612-based designs to the MSP430F261x device family. In the course of this application report
This document provides a vocabulary of French speech data coded in LPC (format D6). This ready-to-use vocabulary is used to generate a vocal output for Date and Time Stamping (DTS) and voice prompts.
The AFEDRI8201 analog front end chip is an IF analog-to-digital converter for AM/FM/HD/DAB/digital radio systems. This article explains how the AFEDRI8201 can support applications such as HD radio™ Eureka DAB and ISDB-TSB. In addition an actual AFEDRI8201 register configuration example is described.
The TMS320TCI6484 has 32KB L1D SRAM 32KB L1P SRAM and 2MB L2 SRAM. A 32-bit 667MHz DDR2 SDRAM interface is provided on the DSP to support up to 512MB of external memory.
Memory access performance is very critical for software running on the DSP. On the TCI6484 DSP all the memories can be accessed by DSP cores and multiple DMA masters.
The DSP core is capable of performing up to 128 bits
Many applications require multiple analog-to-digital converters (ADC) in a system. Daisy chaining multiple ADCs enables the use of a single data receiver or a small FPGA. It offers easy and minimal digital routing. This application report describes how multiple ADCs (ADS8410/13) work in a daisy-chain mode. The device offers a high-speed (200 Mbps) LVDS serial interface. This application report als