High Power, 88 W Peak, Silicon SPDT, Reflective Switch, 0.7 GHz to 4.0 GHz Features: Reflective, 50 design Low insertion loss: 0.7 dB typical to 2.0 GHz High power handling at TCASE = 105°C Long term (>10 years) average CW power: 43 dBm Peak power: 49 dBm LTE average power (8 dB PAR): 41 dBm Single event (<10 sec) average LTE average power (8 dB PAR): 44 dBm High linearity P0.1dB: 47 dBm typical IP3: 70 dBm typical ESD ratings HBM: 4 kV, (Class 3A) CDM: 1.25 kV Single positive supply: 5 V Positive control, CMOS/TTL compatible 32-lead, 5 mm × 5 mm LFCSP package

High Power, 88 W Peak, Silicon SPDT, Reflective Switch, 0.7 GHz to 4.0 GHz Features: Reflective, 50 design Low insertion loss: 0.7 dB typical to 2.0 GHz High power handling at TCASE = 105°C Long term (>10 years) average CW power: 43 dBm Peak power: 49 dBm LTE average power (8 dB PAR): 41 dBm Single event (<10 sec) average LTE average power (8 dB PAR): 44 dBm High linearity P0.1dB: 47 dBm typical IP3: 70 dBm typical ESD ratings HBM: 4 kV, (Class 3A) CDM: 1.25 kV Single positive supply: 5 V Positive control, CMOS/TTL compatible 32-lead, 5 mm × 5 mm LFCSP package

Silicon SPDT Switch, Reflective, 35 GHz to 44 GHz Features:Reflective design Low insertion loss: 1.8 dB at 44 GHz High isolation: 28 dB at 44 GHz High input linearity 0.1 dB power compression (P0.1dB): 37 dBm Third-order intercept (IP3): 52 dBm High RF power handling: 28 dBm average 36 dBm peak Single supply operation: 3.3V Internal negative voltage generator (NVG) RF settling time (0.1 dB final RF output): 45 ns 20-terminal, 3 mm × 3 mm, land grid array package Pin compatible with the ADRF5300: 24 GHz - 32 GHz

High Linearity, Silicon SP4T Switch, 1.8 GHz to 3.8 GHz Features: Reflective design Low Insertion Loss 0.35 dB to 2.8 GHz typical 0.40 dB to 3.8 GHz typical High power handling at TCASE = 105°C Long-term (>10 years) average Continuous wave power: 39 dBm LTE signal Average power: 39 dBm Peak power: 49 dBm High input linearity, IP3: 84 dBm typical ESD ratings HBM: 2000 V, Class 2 CDM: 1000 V, Class C3 Single-supply operation, integrated NVG Positive control, LVCMOS-/LVTTL- compatible 4 mm x 4 mm, 22-terminal LGA package

Die on Carrier, Silicon SPDT Switch, 100 MHz to 60 GHz Features: Ultrawideband frequency range: 100 MHz to 60 GHz Reflective design Bond pads for wire bond and ribbon bond Low insertion loss 1.0 dB typical up to 18 GHz 1.3 dB typical up to 44 GHz 1.5 dB typical up to 55 GHz High input linearity P1dB: 28 dBm typical IP3: 50 dBm typical High RF power handling Through path: 27 dBm up to 40 GHz Hot switching: 27 dBm up to 40 GHz No low frequency spurious signals RF settling time (50% VCTRL to 0.1 dB of final RF output): 17 ns 14-pad, 2.471 mm x 2.571 mm, die on carrier [CHIP]

Die on Carrier, Silicon Digital Attenuator, 0.5 dB LSB, 6-Bit, 100 MHz to 40 GHz Features:Ultrawideband frequency range: 100 MHz to 40 GHzAttenuation range: 31.5 dB with 0.5 dB stepsBond pads for wire bond and ribbon bondLow insertion loss1.7 dB typical up to 18 GHz2.2 dB typical up to 26 GHz3.2 dB typical up to 40 GHzAttenuation accuracy(0.10 + 2.0% of attenuation state) typical up to 26 GHz(0.13 + 1.5% of attenuation state) typical up to 35 GHz(0.30 + 1.5% of attenuation state) typical up to 40 GHzTypical step error0.12 dB typical up to 26 GHz0.30 dB typical up to 35 GHz0.60 dB typical up to 40 GHzHigh input linearityP0.1dB insertion loss state: 31 dBm typicalP0.1dB other attenuation states: 28 dBm typicalIP3: 50 dBm typicalHigh RF power handling26 dBm steady state average31 dBm steady state peakTight distribution in relative phaseNo low frequency spurious signalsSPI and parallel mode control, CMOS/LVTTL compatibleRF amplitude settling time (0.1 dB of final RF output): 250 ns18-pad, 3.171 mm 1.616 mm, die on carrier [CHIP]

Dual-Channel, 3.3 GHz to 4.0 GHz, 20 W Receiver Front End Features: Integrated dual-channel RF front end 2-stage LNA and high power silicon SPDT switch On-chip bias and matching Single-supply operation High power handling at TCASE = 105°C LTE average power (9 dB PAR) full lifetime: 43 dBm Gain High gain mode: 36 dB typical at 3.6 GHz Low gain mode: 17 dB typical at 3.6 GHz Low noise figure High gain mode: 1.05 dB typical at 3.6 GHz Low gain mode: 1.05 dB typical at 3.6 GHz High isolation RXOUT-CHA and RXOUT-CHB: 47 dB typical TERM-CHA and TERM-CHB: 75 dB typical Low insertion loss: 0.5 dB typical at 3.6 GHz High OIP3: 35 dBm typical Power-down mode and low gain mode Low supply current High gain mode: 95 mA typical at 5 V Low gain mode: 48 mA typical at 5 V Power-down mode: 13 mA typical at 5 V Positive logic control 6 mm × 6 mm, 40-lead LFCSP package Pin compatible with the ADRF5515 and the ADRF5519, and the 10 W versions, ADRF5545A and ADRF5549

Dual-Channel, 3.3 GHz to 4.0 GHz, 20 W Receiver Front End Features: Integrated dual-channel RF front end 2-stage LNA and high power silicon SPDT switch On-chip bias and matching Single supply operation Gain High gain mode: 33 dB typical at 3.6 GHz Low gain mode: 16 dB typical at 3.6 GHz Low noise figure High gain mode: 1.0 dB typical at 3.6 GHz Low gain mode: 1.0 dB typical at 3.6 GHz High isolation RXOUT-CHA and RXOUT-CHB: 45 dB typical TERM-CHA and TERM-CHB: 60 dB typical Low insertion loss: 0.45 dB typical at 3.6 GHz High power handling at TCASE = 105°C Full lifetime LTE average power (9 dB PAR): 43 dBm High OIP3 (high gain mode): 32 dBm typical Power-down mode and low gain mode for LNA Low supply current High gain mode: 86 mA typical at 5V Low gain mode: 36 mA typical at 5V Power-down mode: 12 mA typical at 5V Positive logic control 6 mm × 6 mm, 40-lead LFCSP package Pin compatible with the ADRF5545A, 10 W version

Dual-Channel, 2.4 GHz to 4.2 GHz Receiver Front End Features: Integrated dual-channel RF front end 2-stage LNA and high power SPDT switch On-chip bias and matching Single supply operation Gain High gain mode: 32 dB typical at 3.6 GHz Low gain mode: 16 dB typical at 3.6 GHz Low noise figure High gain mode: 1.45 dB typical at 3.6 GHz Low gain mode: 1.45 dB typical at 3.6 GHz High isolation RXOUT-CHA and RXOUT-CHB: 47 dB typical TERM-CHA and TERM-CHB: 52 dB typical Low insertion loss: 0.65 dB typical at 3.6 GHz High power handling at TCASE = 105°C Full lifetime LTE average power (9 dB PAR): 40 dBm Single event (<10 sec operation) LTE average power (9 dB PAR): 43 dBm High OIP3: 32 dBm typical Power-down mode and low gain mode for LNA Low supply current High gain mode: 86 mA typical at 5 V Low gain mode: 36 mA typical at 5 V Power-down mode: 12 mA typical at 5 V Positive logic control 6 mm × 6 mm, 40-lead LFCSP package

Dual-Channel, 3.7 GHz to 5.3 GHz, Receiver Front End Features: Integrated dual-channel RF front end 2-stage LNA and high power SPDT switch On-chip bias and matching Single supply operation Gain High gain mode: 33 dB typical at 4.6 GHz Low gain mode: 18 dB typical at 4.6 GHz Low noise figure High gain mode: 1.6 dB typical at 4.6 GHz Low gain mode: 1.6 dB typical at 4.6 GHz High channel to channel isolation  Between RxOUT-ChA and RxOUT-ChB: 45 dB typical Between TERM-ChA and TERM-ChB: 53 dB typical  Low insertion loss: 0.5 dB typical at 4.6 GHz High power handling at TCASE = 105°C Full lifetime LTE average power (9 dB PAR): 40 dBm Single event (<10 sec operation) LTE average power (9 dB PAR): 43 dBm High OIP3: 31 dBm typical Power-down mode and low gain mode for LNA Low supply current High gain mode: 86 mA typical at 5 V Low gain mode: 36 mA typical at 5 V Power-down mode: 12 mA typical at 5 V Positive logic control 40-lead, 6 mm × 6 mm LFCSP 

0.5 dB LSB, 6-Bit, Silicon Digital Attenuator, 9 kHz to 40 GHz Features: Ultrawideband frequency range: 9 kHz to 40 GHz Attenuation range: 0.5 dB steps to 31.5 dB Low insertion loss with impedance match 2.0 dB up to 18 GHz 2.8 dB up to 26 GHz 4.5 dBup to 40 GHz Attenuation accuracy with impedance match ±(0.20 + 1.0% of attenuation state) up to 18 GHz ±(0.20 + 1.5% of attenuation state) up to 26 GHz ±(0.40+ 3.0% of attenuation state) up to 40 GHz Typical step error with impedance match ±0.25 dB up to 26 GHz ±0.65 dB up to 40 GHz High input linearity P0.1dB insertion loss state: 30 dBm P0.1dB other attenuation states: 27 dBm IP3: 50 dBm typical High RF input power handling: 27 dBm average, 30 dBm peak Tight distribution in relative phase No low frequency spurious signals SPI and parallel mode control, CMOS/LVTTL compatible RF amplitude settling time (0.1 dB of final RF output): 8 µs 24-terminal, 4 mm × 4 mm LGA package Pin-compatible with ADRF5730, fast switching version

2 dB LSB, 4-Bit, Silicon Digital Attenuator, 9 kHz to 40 GHz Features: Ultrawideband frequency range: 9 kHz to 40 GHz Attenuation range: 2 dB steps to 30 dB Low insertion loss 1.6 dB to 18 GHz 2.0 dB to 26 GHz 3.4 dB to 40 GHz Attenuation accuracy ±(0.1 + 1.0%) of attenuation state up to 18 GHz ±(0.1 + 2.5%) of attenuation state up to 26 GHz ±(0.6 + 10.0%) of attenuation state up to 40 GHz Typical step error ±0.15 dB to 18 GHz ±0.20 dB to 26 GHz ±0.60 dB to 40 GHz High input linearity P0.1dB insertion loss state: 30 dBm P0.1dB other attenuation states: 26 dBm IP3: 50 dBm typical High RF input power handling: 26 dBm average, 30 dBm peak Tight distribution in relative phase No low frequency switching spurs SPI and parallel mode control, CMOS/LVTTL compatible RF amplitude settling time (0.1 dB of final RF output): 8.5 μs 2.5 mm × 2.5 mm, 16-terminal LGA package Pin compatible with ADRF5731, fast switching version

0.5 dB LSB, 6-Bit, Silicon Digital Attenuator, 100 MHz to 40 GHz Features:Ultrawideband frequency range: 100 MHz to 40 GHz Attenuation range: 0.5 dB steps to 31.5 dB Low insertion loss with impedance match 2.1 dB up to 18 GHz 2.9 dB up to 26 GHz 4.8 dB up to 40 GHz Attenuation accuracy with impedance match ±(0.10 + 1.0% of attenuation state) up to 18 GHz ±(0.15 + 0.8% of attenuation state) up to 26 GHz ±(0.35 + 2.5% of attenuation state) up to 40 GHz Typical step error with impedance match ±0.18 dB up to 18 GHz ±0.23 dB up to 26 GHz ±0.51 dB up to 40 GHz High input linearity P0.1dB insertion loss state: 30 dBm P0.1dB other attenuation states: 27 dBm IP3: 50 dBm typical High RF input power handling: 27 dBm average, 30 dBm peak Tight distribution in relative phase No low frequency spurious signals SPI and parallel mode control, CMOS/LVTTL compatible RF settling time (0.1 dB of final RF output): 250 ns 24-terminal, 4 mm × 4 mm LGA package Pin compatible with ADRF5720, low frequency cutoff version

2 dB LSB, 4-Bit, Silicon Digital Attenuator, 10 MHz to 60 GHz Features: Ultrawideband frequency range: 10 MHz to 60 GHz Attenuation range: 2 dB steps to 22 dB Low insertion loss 1.4 dB up to 20 GHz 2.2 dB up to 44 GHz 3.3 dB up to 55 GHz Attenuation accuracy (0.1 + 1.0% of state) up to 20 GHz (0.2 + 3.0% of state) up to 44 GHz (0.2 + 7.0% of state) up to 55 GHz Typical step error 0.30 dB up to 20 GHz 0.50 dB up to 44 GHz 0.60 dB up to 55 GHz High input linearity P0.1dB: 25.5 dBm typical IP3: 45 dBm typical High RF input power handling: 24 dBm average, 24 dBm peak Tight distribution in relative phase No low frequency spurious signals Parallel mode control, CMOS and LVTTL compatible RF amplitude settling time (0.1 dB of final RF output): 175 ns/li> 16-terminal, 2.5 mm 2.5 mm, RoHS compliant LGA package

2 dB LSB, 4-Bit, Silicon Digital Attenuator, 10 MHz to 60 GHz Features: Ultrawideband frequency range: 10 MHz to 60 GHz Attenuation range: 2 dB steps to 22 dB Low insertion loss 1.4 dB up to 20 GHz 2.2 dB up to 44 GHz 3.3 dB up to 55 GHz Attenuation accuracy (0.1 + 1.0% of state) up to 20 GHz (0.2 + 3.0% of state) up to 44 GHz (0.2 + 7.0% of state) up to 55 GHz Typical step error 0.30 dB up to 20 GHz 0.50 dB up to 44 GHz 0.60 dB up to 55 GHz High input linearity P0.1dB: 25.5 dBm typical IP3: 45 dBm typical High RF input power handling: 24 dBm average, 24 dBm peak Tight distribution in relative phase No low frequency spurious signals Parallel mode control, CMOS and LVTTL compatible RF amplitude settling time (0.1 dB of final RF output): 175 ns/li> 16-terminal, 2.5 mm 2.5 mm, RoHS compliant LGA package

2 dB LSB, 4-Bit, Silicon Digital Attenuator, 10 MHz to 60 GHz Features: Ultrawideband frequency range: 10 MHz to 60 GHz Attenuation range: 2 dB steps to 22 dB Low insertion loss 1.4 dB up to 20 GHz 2.2 dB up to 44 GHz 3.3 dB up to 55 GHz Attenuation accuracy (0.1 + 1.0% of state) up to 20 GHz (0.2 + 3.0% of state) up to 44 GHz (0.2 + 7.0% of state) up to 55 GHz Typical step error 0.30 dB up to 20 GHz 0.50 dB up to 44 GHz 0.60 dB up to 55 GHz High input linearity P0.1dB: 25.5 dBm typical IP3: 45 dBm typical High RF input power handling: 24 dBm average, 24 dBm peak Tight distribution in relative phase No low frequency spurious signals Parallel mode control, CMOS and LVTTL compatible RF amplitude settling time (0.1 dB of final RF output): 175 ns/li> 16-terminal, 2.5 mm 2.5 mm, RoHS compliant LGA package

Dual Programmable Filters and VGAs for 2 GHz Channel Spacing forW Radios Features: Matched VGAs and programmable filters Maximum gain: 53 dB Continuous gain control range: 60 dB Filter bypass mode I/Q bandwidth ±1 dB gain flatness: >1250 MHz 4-pole Butterworth filter I/Q bandwidth: 36 MHz to 720 MHz RMS detector IMD3: <−55 dBc for 1.5 V p-p composite output HD2, HD3: <−55 dBc for 1.5 V p-p output Noise figure: 10.5 dB at maximum gain NF < 11 dB over 12 dB of VGA2 gain backoff 100 differential input, low impedance output Optional dc output offset correction SPI-programmable filter corners Single 3.3 V supply operation with power-down feature

Low Frequency to 3 GHz, Dual VGA with Output Common-Mode and DC Offset Control Features: Dual, matched VGAs Maximum voltage gain: 18 dB Gain control attenuation range: 21 dB typical for TA = 25°C ±1 dB gain flatness bandwidth: 2.5 GHz typical IMD2 and IMD3 (1.5 V p-p output level) −56.8 dBc typical and −75 dBc typical, respectively, at VGN = 1.5 V, 980 MHz and 1000 MHz tones HD2 and HD3 (1.5 V p-p output level) −75 dBc typical and −73.7 dBc typical, respectively, at VGN = 1.5 V, fundamental at 500 MHz −55.9 dBc typical and −57.5 dBc typical, respectively, at VGN = 1.5 V, fundamental at 1 GHz Noise figure: 10.5 dB typical at maximum gain and at 500 MHz 14.8 dB at maximum gain and at 2 GHz Noise figure decreases dB for dB with gain backoff 100 differential input impedance ≤ 16 differential output impedance Programmable Output DC offset nominal range: ± 400 mV Output common-mode control: > ± 200 mV for VOCM = ±0.2 V Single- or dual-supply operation with power-down feature Single supply: VPOS = 5 V, VNEG = 0 V (nominal) Dual supply: VPOS = 3 V, VNEG = −2 V (nominal)

Dual Downconverter with DVGA and PLL/VCO, 450 MHz to 2700 MHz Features:Dual down-converter with integrated fractional-N PLL/VCORF: 450 MHz to 2700 MHz continuousLO frequency: 450 MHz to 2900 MHz, high-side or low-side injection43 dB gain control rangeGain control with up/down and SPIIntegrated RF balun for single-ended 50 inputsPower supply: 3.3 and 5 V8 mm 8 mm, 56-lead LFCSP package

5.9 GHz to 23.6 GHz, Wideband, Microwave Upconverter Features: Wideband RF output frequency range: 5.9 GHz to 23.6 GHz Two upconversion modes Direct conversion from baseband I/Q to RF Single sideband upconversion from real IF LO input frequency range: 5.4 GHz to 14 GHz LO doubler for up to 28 GHz Matched 100 Ω balanced RF output, LO input, and IF input High impedance baseband inputs Sideband suppression and carrier feedthrough optimization Variable attenuator and power detector for Tx power control Programmable via 4-wire SPI interface 32-lead, 5 mm × 5 mm LFCSP microwave packaging