RF Switch ICs DC-4 GHZ Hi Isolation Switch

Digital to Analog Converters - DAC 12-Bit Precision DAC

The ADPD105/ADPD106/ADPD107 are highly efficient,photometric front ends, each with an integrated 14-bit analog-to-digitalconverter (ADC) and a 20-bit burst accumulator thatworks with flexible light emitting diode (LED) drivers. Theaccumulator is designed to stimulate an LED and measurethe corresponding optical return signal. The data output andfunctional configuration occur over a 1.8 V I2C interface on theADPD105 or SPI on the ADPD106 and ADPD107. The controlcircuitry includes flexible LED signaling and synchronousdetection.The analog front end (AFE) features best-in-class rejection of signaloffset and corruption due to modulated interference commonlycaused by ambient light.Couple the ADPD105/ADPD106/ADPD107 with a lowcapacitance photodiode of

The AD5590 is a 16-channel input and 16-channel output analog I/O port with eight uncommitted amplifiers, operating from a single 4.5 V to 5.25 V supply. The AD5590 comprises 16 input channels multiplexed into a 1 MSPS, 12-bit successive approximation ADC with a sequencer to allow a preprogrammed selection of channels to be converted sequentially. The ADC contains a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 1 MHz.The conversion process and data acquisition are controlled using ASYNC and the serial clock signal, allowing the device to easily interface with microprocessors or DSPs. The input signal is sampled on the falling edge of ASYNC and conversion is also initiated at this point. There are no pipeline delays associated with the ADC. By setting the relevant bits in the control register, the analog input range for the ADC can be selected to be a 0 V to VREFA input or a 0 V to 2 ? VREFA with either straight binary or twos complement output coding. The conversion time is determined by the ASCLK frequency because it is also used as the master clock to control the conversion.The DAC section of the AD5590 comprises sixteen 12-bit DACs divided into two groups of eight. Each group has an on-chip reference. The on-board references are off at power-up, allowing the use of external references. The internal references are enabled via a software write.The AD5590 incorporates a power-on reset circuit that ensures that the DAC outputs power up to 0 V and remain powered up at this level until a valid write takes place. The DAC contains a power-down feature that reduces the current consumption of the device and provides software-selectable output loads while in power-down mode for any or all DAC channels. The outputs of all DACs can be updated simultaneously using the LDAC function, with the added functionality of user-selectable DAC channels to simultaneously update. There is also an asynchronous CLR that updates all DACs to a user-programmable code: zero scale, midscale, or full scale.The AD5590 contains eight low noise, single-supply amplifiers. These amplifiers can be used for signal conditioning for the ADCs, DACs, or other independent circuitry, if required.APPLICATIONS Optical Line Cards (Monitoring and Control) Base Stations General Purpose Analog I/O Monitoring and control

The ADV7180 automatically detects and converts standard analog baseband television signals compatible with worldwide NTSC, PAL, and SECAM standards into 4:2:2 component video data compatible with the 8-bit ITU-R BT.656 interface standard.The simple digital output interface connects gluelessly to a wide range of MPEG encoders, codecs, mobile video processors, and Analog Devices, Inc., digital video encoders, such as the ADV7391. External HS, VS, and FIELD signals provide timing references for LCD controllers and other video ASICs, if required. Accurate 10-bit analog-to-digital conversion provides professional quality video performance for consumer applications with true 8-bit data resolution. Three analog video input channels accept standard composite, S-video, or component video signals, supporting a wide range of consumer video sources. AGC and clamp-restore circuitry allow an input video signal peak-to-peak range to 1.0 V. Alternatively, these can be bypassed for manual settings.The line-locked clock output allows the output data rate, timing signals, and output clock signals to be synchronous, asynchronous, or line locked even with ?5% line length variation. Output control signals allow glueless interface connections in many applications. The ADV7180 is programmed via a 2-wire, serial bidirectional port (I2C? compatible) and is fabricated in a 1.8 V CMOS process. Its monolithic CMOS construction ensures greater functionality with lower power dissipation. LFCSP package options makes the decoder ideal for space-constrained portable applications. A 64-lead LQFP package is pin compatible with the ADV7181C.The 48-Lead LQFP, 40-lead LFCSP, and 32-lead LFCSP use one pin to output VS or FIELD.APPLICATIONS Digital camcorders and PDAs Low cost SDTV PIP decoder for digital TVs Multichannel DVRs for video security AV receivers and video transcoding PCI-/USB-based video capture and TV tuner cards Personal media players and recorders Smartphone/multimedia handsets In-car/automotive infotainment units Rearview camera/vehicle safety systems

The AD7606C-18 is an 18-bit, simultaneous sampling, analog-to-digital data acquisition system (DAS) with eight channels. Each channel contains analog input clamp protection, a programmable gain amplifier (PGA), a low-pass filter (LPF), and an 18-bit successive approximation register (SAR) analog-to-digital converter (ADC). The AD7606C-18 also contains a flexible digital filter, a low drift, 2.5 V precision reference, a reference buffer to drive the ADC, and flexible parallel and serial interfaces.The AD7606C-18 operates from a single 5 V supply and accommodates the following input ranges when sampling at throughput rates of 1 MSPS for all channels: Bipolar single-ended: ?12.5 V, ?10 V, ?6.25 V, ?5 V, and ?2.5 V Unipolar single-ended: 0 V to 12.5 V, 0 V to 10 V, and 0 V to 5 V Bipolar differential: ?20 V, ?12.5 V, ?10 V, and ?5 VThe input clamp protection tolerates voltages up to ?21 V. The single supply operation, on-chip filtering, and high input impedance eliminate the need for external driver op amps, which require bipolar supplies. For applications with lower throughput rates, the AD7606C-18 flexible digital filter can be used to improve noise performance.In hardware mode, the AD7606C-18 is fully compatible with the AD7608 and AD7609. In software mode, the following advanced features are available: Analog input range selectable per channel with added ranges available High bandwidth mode (220 kHz) selectable per channel Additional oversampling options with an oversampling ratio up to 256 System gain, system offset, and system phase calibration, per channel Analog input open circuit detector Diagnostic multiplexer Monitoring functions (serial peripheral interface (SPI) invalid read and write, cyclic redundancy check (CRC), busy stuck monitor, and reset detection)Note that throughout the data sheet, multifunction pins, such as the RD/SCLK pin, are referred to either by the entire pin name or by a single function of the pin, for example, the SCLK pin, when only that function is relevant.APPLICATIONSPower line monitoringProtective relaysMultiphase motor controlInstrumentation and control systemsData acquisition systems

The HMC728 is a 2:1 Selector designed to support data transmission rates of up to 13 Gbps, and selector port operation of up to 13 GHz. The selector routes one of the two single-ended inputs to the differential output upon assertion of the proper select port. All single-ended input signals to the HMC728 are terminated with 50 ohms to ground on-chip, and may be either AC or DC coupled.The outputs of the HMC728 may be operated either differentially or single-ended. Outputs can be connected directly to a 50 ohm terminated system, while DC blocking capacitors may be used if the terminating system is 50 ohms to a non-ground DC voltage. The HMC728 operates from a single -3.3V DC supply and is available in a ceramic RoHS compliant 3x3 mm SMT package.APPLICATIONS 2:1 Multiplexer up to 13 Gbps F ATE Applications Broadband Test & Measurement Serial Data Transmission up to 13 Gbps Redundant Path Switching Built-in Test

The AD8155 is an asynchronous, protocol-agnostic, dual-lane 2:1 switch with a total of six differential CML inputs and six differential CML outputs. The signal path supports NRZ signaling with data rates up to 6.5 Gbps per lane. Each lane offers programmable receive equalization, programmable output pre-emphasis, programmable output levels, and loss-of-signal detection.The nonblocking switch-core of the AD8155 implements a 2:1 multiplexer and 1:2 demultiplexer per lane and supports independent lane switching through the two select pins, SEL[1:0]. Each port is a two-lane link. Every lane implements an asynchronous path supporting dc to 6.5 Gbps NRZ data, fully independent of other lanes. The AD8155 has low latency and very low lane-to-lane skew.The main application of the AD8155 is to support redundancy on both the backplane and the line interface sides of a serial link. The demultiplexing path implements unicast and bicast capability, allowing the part to support either 1+1 or 1:1 redundancy.The AD8155 is also suited for testing high speed serial links because of its ability to duplicate incoming data. In a port monitoring application, the AD8155 can maintain link connectivity with a pass-through connection from Port C to Port A while sending a duplicate copy of the data to test equipment on Port B.The rich feature set of the AD8155 can be controlled either through external toggle pins or by setting on-chip control registers through the I2C? interface.ApplicationsLow cost redundancy switchSONET OC48/SDH16 and lower data ratesRXAUI, 4x Fibre Channel, Infiniband , and GbE over backplaneOIF CEI 6.25 Gbps over backplaneSerial data-level shift2-/4-/6-lane equalizers or redrivers

Demonstration circuit 2807A features the LTC6560 single channel transimpedance amplifier (TIA) with output multiplexing. The DC2807A accepts voltage pulses and converts them to current for the TIA. The LTC6560, which features 74kΩ transimpedance gain and 30µA linear input current range, is ideal for LIDAR receivers using avalanche photodiodes (APD). The LTC6560 operates from 5V single supply and consumes only 90mW. Utilizing the LTC6560’s output MUX, multiple LTC6560 devices can combine into a single output. The LTC6560’s fast overload recovery makes it well suited for LIDAR receivers. The LTC6560’s single-ended output can swing 2VP-P into a 100Ω load. The LTC6560 is packaged in a compact 3mm × 3mm 16-pin leadless QFN package with an exposed pad for thermal management and low inductance.

The ADG901/ADG902 are wideband switches that use a complementary metal-oxide semiconductor (CMOS) process to provide high isolation and low insertion loss to 1 GHz. The ADG901 is an absorptive (matched) switch with 50 ? terminated shunt legs, while the ADG902 is a reflective switch. These devices are designed such that the isolation is high over the dc to 1 GHz frequency range. These switches enable the user to pass dc signals up to 0.5 V without the use of a dc blocking capacitor. They have on-board CMOS control logic, thus eliminating the need for external controlling circuitry. The control inputs are both CMOS and LVTTL compatible. The low power consumption of these CMOS devices makes them ideally suited to wireless applications and general-purpose high frequency switching.Product Highlights 40 dB Off Isolation at 1 GHz 0.8 dB Insertion Loss at 1 GHz 17 dBm P1dB at 1 GHzApplications Wireless communications General purpose RF switching Dual-band applications High speed filter selection Digital transceiver front-end switch IF switching Tuner modules Antenna diversity switching list

The ADV8003 is a multiple input video signal processor that can de-interlace and scale SD, ED, or HD video data to HD formats, generate a bitmap on-screen display (OSD) and output the video with OSD overlaid on two High Definition Multimedia Interface (HDMI) transmitters and a video encoder.Video can be input into the ADV8003 in a number of ways: using the 48-bit TTL pixel port, using the 24-bit external OSD TTL pixel port, or from a device with a HDMI transmitter such as the ADV7850. The ADV8003 supports many of the formats outlined in the CEA-861 and VESA specifications, as well as several other widely used timing formats.Using two external DDR2 memories, the ADV8003 can perform high performance, motion adaptive interlaced to progressive conversion on SD and HD content. Using a single DDR2 memory, the HD de-interlacing is limited to intrafield.The ADV8003 features primary and secondary video scalers that enable simultaneous output of multiple different resolutions. Detail enhancement and image enhancing techniques such as random, mosquito, and block noise reduction allow for improved final image quality. The frame rate converter of the ADV8003 allows the conversion between common frame rates with support to output two different frame rates simultaneously under certain conditions.The ADV8003 has a flexible digital core that allows the user to configure the part in several different modes: using a single video processing channel, using dual video processing channels, or displaying OSD on multiple outputs of different resolutions. The ADV8003 can accept OSD information from either an external OSD source on the 24-bit external OSD TTL pixel data input or internally generate a high quality, bitmap-based OSD. The internal OSD is highly flexible and allows the system designer to easily incorporate features like scrolling text and animation in various color depths up to 24-bit true color.Analog Devices, Inc., provides an OSD development tool (Blimp) to assist in the design, debug, and emulation of the OSD prior to integration with the system application. When the design is complete, the OSD development tool automatically generates code to which system APIs can be added before integration with the system application and an OSD design resource, which must be downloaded to an external SPI flash memory.Video can be output from the ADV8003 using one or both of the HDMI transmitters and/or the 6-DAC SD/HD video encoder. The flexible multiplexing in the part allows simultaneous output of HD formats on the HDMI transmitters and on the HD DACs (for example, 1080p) with SD formats on the SD DACs (for example, 480i).Both of the HDMI transmitters on the ADV8003 support all mandatory and many optional 3D video resolutions and audio return channels (ARC). Each transmitter also features a full CEC master. The ADV8003 can receive up to six channels of I2S, S/PDIF, direct stream digital (DSD), and high bit rate (HBR). The six 12-bit NSV? video DACs allow for composite (CVBS), S-Video (Y/C), and component (YPrPb) analog outputs in standard, enhanced, and high definition video formats. Oversampling of 216 MHz (SD and ED) and 297 MHz (HD) removes the requirement for external output filtering.The ADV8003 can also support 30-bit TTL in and 30-bit TTL out mode for professional applications.The ADV8003 supports the I2C? protocol for communication with the system microcontroller.APPLICATIONS High end A/V receivers Upconverting DVD players/recorders Blu-ray players/recorders Set-top boxes Video conferencing Standalone video processors HDMI splitters

The AD5674/AD5674R/AD5679/AD5679R are low power,?16-channel, 12-/16-bit, buffered voltage output, digital-to-analog converters (DACs) that include a 2.5 V, 2 ppm/?C internal reference (enabled by default), and a gain select pin, resulting in a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The?devices operate from a single, 2.7 V to 5.5 V supply range and?are guaranteed monotonic by design. The AD5674/AD5674R/AD5679/AD5679R are available in a 28-lead lead frame chip scale package (LFCSP) and incorporate a power-on reset (POR) circuit that ensures that the DAC outputs power up to and remains at zero-scale or midscale until a valid write. The AD5674/AD5674R/AD5679/AD5679R contain a power-down mode that reduces the current?consumption to 2 ?A typical.Product Highlights High channel density: 16 channels in 4 mm ? 4 mm?LFCSP. High relative accuracy (integral nonlinearity (INL)) ?4 LSB maximum. Low drift, 2.5 V, on-chip reference.Applications Optical transceivers Base station power amplifiers Process control (programmable logic controller (PLC) input/output cards) Industrial automation Data acquisition systems

The LTM4681 is a quad 31.25A or single 125A stepdown??Module? (power module) DC/DC regulator featuring?remote configurability and telemetry-monitoring?of power management parameters over PMBus. The?LTM4681 is comprised of digitally programmable analog?control loops, precision mixed-signal circuitry, EEPROM,?power MOSFETs, inductors and supporting components.The LTM4681?s 2-wire serial interface allows outputs?to be margined, tuned and ramped up and down at programmable?slew rates with sequencing delay times. True input current sense, output currents and voltages, output?power, temperatures, uptime and peak values are readable. Custom configuration of the EEPROM contents is not?required. At start-up, output voltages, switching frequency,?and channel phase angle assignments can be set by pinstrapping?resistors. The LTpowerPlay? GUI and DC1613?USB-to-PMBus converter and demo kits are available.?The LTM4681 is offered in a 15mm ? 22mm ? 8.17mm?BGA package available with SnPb or RoHS compliant?terminal finish.APPLICATIONS Multi-Rail Processor Power, Configurable Core Power

RF Switch ICs GaAs MMIC SP4T Non-Reflective, DC-20

The HMC835LP6GE is a low noise, wide band, Fractional-N PLL that features an integrated VCO with a fundamental frequency of 2020 to 4100 MHz, and an integrated VCO Output Divider (divide by 2/4/6/.../60/62) that together enable the HMC835LP6GE to generate frequencies from 33 MHz to 4100 MHz. Integrated Phase Detector (PD) and a deltasigma modulator capable of operating at up to 100 MHz enable wider loop-bandwidths, faster frequency changes along with excellent spectral performance.Two independent RF outputs, with independent gain control, enable the HMC835LP6GE to distribute identical frequency and phase signals to multiple destinations, at optimal signal levels tailored to each output.External VCO input, allows the HMC835LP6GE to lock external VCOs, and enables cascaded LO architectures for MIMO radio applications. Two separate Charge Pump (CP) outputs enable separate loop filters optimized for both integrated and external VCOs, and seamless switching between integrated or external VCOs during operation. Programmable RF output phase feature can further phase adjust and synchronize multiple HMC835LP6GEs enabling scalable MIMO and beam-forming radio architectures.Additional features include configurable output mute function that mutes RF outputs during frequency changes, Exact Frequency Mode that enables the HMC835LP6GE to generate fractional frequencies with 0 Hz frequency error, and the ability to synchronously change frequencies without changing the phase of the output signal.Applications MIMO Radio Architectures Cellular Infrastructure Cellular backhaul Communications Test Equipment CATV Equipment Phased Array Applications? DDS Replacement

The AD5724R/AD5734R/AD5754R are quad, 12-/14-/16-bit serial input, voltage output, digital-to-analog converters (DACs). They operate from single supply voltages of +4.5 V up to +16.5 V or dual supply voltages from ?4.5 V up to ?16.5 V. Nominal full-scale output range is software selectable from +5 V, +10 V, +10.8 V, ?5 V, ?10 V, or ?10.8 V. Integrated output amplifiers, reference buffers, and proprietary power-up/power-down control circuitry are also provided.The devices offer guaranteed monotonicity, integral nonlinearity (INL) of ?16 LSB maximum, low noise, 10 ?s typical settling time, and an on-chip +2.5 V reference.The AD5724R/AD5734R/AD5754R use a serial interface that operates at clock rates up to 30 MHz and are compatible with DSP and microcontroller interface standards. Double buffering allows the simultaneous updating of all DACs. The input coding is user-selectable twos complement or offset binary for a bipolar output (depending on the state of Pin BIN/2sCOMP) and straight binary for a unipolar output. The asynchronous clear function clears all DAC registers to a user-selectable zero-scale or mid-scale output. The parts are available in a 24-lead TSSOP and offer guaranteed specifications over the ?40?C to +85?C industrial temperature range.Applications Industrial automation Closed-loop servo control, process control Automotive test and measurement Programmable logic controllers

The HMC822LP6CE is a fully functioned Fractional-N Phase-Locked-Loop (PLL) Frequency Synthesizer with an Integrated Voltage Controlled Oscillator (VCO). The synthesizer consists of an integrated low noise VCO with a triband output, an autocalibration subsystem for low voltage VCO tuning, a very low noise digital Phase Detector (PD), a precision controlled charge pump, a low noise reference path divider and a fractional divider.The fractional synthesizer features an advanced delta-sigma modulator design that allows both ultra-fine step sizes and low spurious products. The phase detector (PD) features cycle slip prevention (CSP) technology to allow faster frequency hopping times. Ultra low in-close phase noise and low spurious also allows wider loop bandwidths for faster frequency hopping and low micro-phonics.For theory of operation and register map refer to the 'PLLs with Integrated VCO - RF VCOs' Operating Guide.Applications Cellular/4G Infrastructure Repeaters and Femtocells Communications Test Equipment CATV Equipment Phased Array Applications DDS Replacement? Very High Data Rate Radios

The HMC820LP6CE is a fully functioned Fractional-N Phase-Locked-Loop (PLL) Frequency Synthesizer with an Integrated Voltage Controlled Oscillator (VCO). The synthesizer consists of an integrated low noise VCO with a triband output, an autocalibration subsystem for low voltage VCO tuning, a very low noise digital Phase Detector (PD), a precision controlled charge pump, a low noise reference path divider and a fractional divider.The fractional synthesizer features an advanced delta-sigma modulator design that allows both ultra-fine step sizes and low spurious products. The phase detector (PD) features cycle slip prevention (CSP) technology to allow faster frequency hopping times. Ultra low in-close phase noise and low spurious also allows wider loop bandwidths for faster frequency hopping and low micro-phonics.For theory of operation and register map refer to the 'PLLs with Integrated VCO - RF VCOs' Operating Guide.Applications Cellular/4G Infrastructure Repeaters and Femtocells Communications Test Equipment CATV Equipment Phased Array Applications DDS Replacement? Very High Data Rate Radios