The ADRF5045 is a general-purpose, single-pole, four-throw (SP4T) switch manufactured using a silicon process. It comes in a 24-terminal land grid array (LGA) package and provides high isolation and low insertion loss from 9 kHz to 30 GHz.This broadband switch requires dual supply voltages, +3.3 V and ?3.3 V, and provides complementary metal-oxide semiconductor (CMOS)/low voltage transistor-transistor logic (LVTTL) logiccompatible control.Applications Test instrumentation Microwave radios and very small aperture terminals (VSATs) Military radios, radars, and electronic counter measures (ECMs) Broadband telecommunications systems

The ADRF5047 is a reflective, single-pole, four-throw (SP4T) switch manufactured in the silicon process.The ADRF5047 operates from 9 kHz to 44 GHz with an insertion loss of lower than 2.7 dB and an isolation of higher than 31 dB. The device has a radio frequency (RF) input power handling capability of 26.5 dBm for both through path and hot switching.The ADRF5047 draws a low current of 3 ?A on the positive supply of +3.3 V, and ?110 ?A on the negative supply of ?3.3 V. The device provides complementary metal-oxide semiconductor (CMOS)-/low voltage transistor-transistor logic (LVTTL)-compatible controls.The ADRF5047 is pin-compatible with the ADRF5046 fast switching version, which operates from 100 MHz to 44 GHz.The ADRF5047 comes in a 20-terminal, 3 mm ? 3 mm, RoHS-compliant, land grid array (LGA) package and operates from ?40?C to +105?C.Applications Industrial scanner Test instrumentation Cellular infrastructure?mmWave 5G Military radios, radars, and electronic counter measures (ECMs) Microwave radios and very small aperture terminals (VSATs)

The ADRF5141 is a reflective, single pole double-throw (SPDT) switch manufactured in the silicon process. It is used in transmit-receive (T/R) applications with an integrated power limiter at the receive side. The ADRF5141 operates from 8 GHz to 12 GHz. The RX arm with the integrated power limiter has a limiting capability of 18 dBm output power (TBC) with a low insertion loss of 1.3 dB at 10 GHz while the TX arm has an insertion loss of 0.9 dB at 10 GHz. The ADRF5141 draws a low current of 13 ?A on the positive supply of +3.3 V and 360 ?A on negative supply of ?3.3 V. The device employs complementary metal-oxide semiconductor (CMOS)-/low voltage transistor to transistor logic (LVTTL)-compatible controls. The ADRF5141 requires no additional driver circuitry, making it an ideal alternative to GaN and PIN diode-based switches. The ADRF5141 comes in a 20-lead, 3.0 mm ? 3.0 mm, RoHS-compliant, land grid array (LGA) package and can operate from ?40?C to +85?.APPLICATIONSElectronic warfareMilitary radios, radars, and electronic counter measuresGaN and PIN diode replacement

The ADRF5250 is a general-purpose, single-pole, five-throw (SP5T), nonreflective switch manufactured using a silicon process. The ADRF5250 is available in a 4 mm ? 4 mm, 24-lead lead frame chip scale package (LFCSP) and provides high isolation and low insertion loss from 100 MHz to 6 GHz.The ADRF5250 incorporates a negative voltage generator to operate with a single positive supply voltage from 3.3 V to 5 V applied to the VDD pin when the VSS pin is connected to ground. The negative voltage generator can be disabled when an external negative supply voltage of ?3.3 V is applied to the VSS pin. The ADRF5250 provides a 1.8 V logic-compatible, 3-pin control interface.Applications Cellular/4G infrastructure Wireless infrastructure Mobile radios Test equipment

The ADRF5300 is a reflective, SPDT switch manufactured in the silicon process.The ADRF5300 is developed for 5G applications ranging from 24 GHz to 32 GHz. The ADRF5300 has a low insertion loss of 1.1 dB, a high isolation of 38 dB, and an RF input power handling capability of 28 dBm average and 36 dBm peak.The ADRF5300 incorporates a negative voltage generator (NVG) to operate with a single positive supply of 3.3 V (VDD) applied to the VDD pin. The device employs CMOS- and low voltage transistor to transistor logic (LVTTL)-compatible controls.The ADRF5300 is packaged in a 20-terminal, 3 mm ? 3 mm, RoHS-compliant, land grid array (LGA) package and can operate from ?40?C to +105?C.APPLICATIONSIndustrial scannerTest instrumentationCellular infrastructure: 5G millimeter waveMilitary radios, radars, electronic counter measures (ECMs)Microwave radios and very small aperture terminals (VSATs)

The ADRF5301 is a reflective, single-pole, double-throw (SPDT) switch manufactured in the silicon process.The ADRF5301 was developed for 5G applications from 35 GHz to 44 GHz. This device has low insertion loss of 1.8 dB, high isolation of 28 dB, and radio frequency (RF) input power handling capability of 28 dBm average and 36 dBm peak.The ADRF5301 incorporates a negative voltage generator (NVG) to operate with a single positive supply of 3.3 V applied to the VDD pin. The devices employs complementary metal-oxide semiconductor (CMOS)-/low voltage transistor to transistor logic (LVTTL)-compatible control.The ADRF5301 is pin-compatible with the ADRF5300, which operates from 24 GHz to 32 GHz.The ADRF5301 comes in a 20-terminal, 3 mm ? 3 mm, RoHS-compliant, land grid array (LGA) package and can operate from ?40?C to +105?C.Applications Industrial scanner Test instrumentation Cellular infrastructure mmWave 5G Military radios, radars, electronic counter measures (ECMs) Microwave radios and very small aperture terminals (VSATs) ?

The ADRF5345 is a high linearity, reflective, single-pole, four-throw (SP4T) switch manufactured in the silicon process.The ADRF5345 operates from 1.8 GHz to 3.8 GHz with a typical insertion loss lower than 0.40 dB and a typical input IP3 of 84 dBm. The device has an RF input power handling capability of 39 dBm for continuous wave signals and 39 dBm average and 49 dBm peak for long-term evolution (LTE) signals.The ADRF5345 incorporates an integrated negative voltage generator (NVG) to operate with a single positive supply of 5 V (VDD) applied to the VDD pin drawing a 2 mA supply current. The device employs low voltage complementary metal-oxide semiconductor (LVCMOS)-/low voltage transistor to transistor logic (LVTTL)- compatible controls.The ADRF5345 comes in a 4 mm ? 4 mm, 22-terminal, RoHS-compliant, land grid array (LGA) package and operates between ?40?C to +105?C.APPLICATIONS5G antenna tiltingWireless infrastructureMilitary and high reliability applicationsTest equipmentPin diode replacement

The ADRF5515A is a dual-channel, integrated RF, front-end, multichip module designed for time division duplexing (TDD) applications. The device operates from 3.3 GHz to 4.0 GHz. The ADRF5515A is configured in dual channels with a cascading, two-stage low noise amplifier (LNA) and a high-power silicon singlepole, double-throw (SPDT) switch.In high gain mode, the cascaded two-stage LNA and switch offer a low noise figure of 1.05 dB and a high gain of 36 dB at 3.6 GHz, with an output third-order intercept (OIP3) point of 35 dBm (typical). In low gain mode, one stage of the two-stage LNA is in bypass, providing 17 dB of gain at a lower current of 48 mA. In power-down mode, the LNAs are turned off and the device draws 13 mA.In transmit operation, when RF inputs are connected to a termination pin (TERM-CHA or TERM-CHB), the switch provides low insertion loss of 0.5 dB and handles long-term evolution (LTE) average power (9 dB peak to average ratio (PAR)) of 43 dBm for full lifetime operation.The device comes in an RoHS-compliant, compact, 6 mm ? 6 mm, 40-lead lead frame chip scale package (LFCSP).APPLICATIONWireless infrastructureTDD massive multiple input and multiple output and active antenna systemsTDD-based communication systems

The ADRF5515 is a dual-channel, integrated RF, front-end, multichip module designed for time division duplexing (TDD) applications. The device operates from 3.3 GHz to 4.0 GHz. The ADRF5515 is configured in dual channels with a cascading, two-stage, LNA and a high power silicon SPDT switch.In high gain mode, the cascaded two-stage LNA and switch offer a low noise figure of 1.0 dB and a high gain of 33 dB at 3.6 GHz with an output third-order intercept point (OIP3) of 32 dBm (typical). In low gain mode, one stage of the two-stage LNA is in bypass, providing 16 dB of gain at a lower current of 36 mA. In power-down mode, the LNAs are turned off and the device draws 12 mA.In transmit operation, when RF inputs are connected to a termination pin (TERM-CHA or TERM-CHB), the switch provides low insertion loss of 0.45 dB and handles long-term evolution (LTE) average power (9 dB peak to average ratio (PAR)) of 43 dBm for full lifetime operation.The ADRF5515 is pin-compatible with the ADRF5545A, 10 W version, which operates from 2.4 GHz to 4.2 GHz.The ADRF5515 does not require any matching components at the RF ports that are internally matched to 50 ?. The ANT and TERM ports are also internally ac-coupled. Therefore, only receiver ports require external dc blocking capacitors.The device comes in an RoHS compliant, compact, 6 mm ? 6 mm, 40-lead LFCSP package.?Applications Wireless infrastructure TDD massive multiple input and multiple output and active antenna systems TDD-based communications systems

The ADRF5547 is a dual-channel, integrated RF, front end multichip module designed for time division duplexing (TDD) applications that operates from 3.7 GHz to 5.3 GHz. The ADRF5547 is configured in dual channels with a cascading twostage low noise amplifier (LNA) and a high power silicon, single-pole, double-throw (SPDT) switch.In high gain mode, the cascaded, two-stage LNA and switch offer a low noise figure of 1.6 dB and high gain of 33 dB at 4.6 GHz with an output third order intercept point (OIP3) of 31 dBm (typical).In low gain mode, one stage of the two-stage LNAs is in bypass, providing 18 dB gain at lower current of 36 mA. In power-down mode, the LNAs are turned off and the device draws 12 mA.?In transmit operation, when RF inputs are connected to a termination pin (TERM-ChA or TERM-ChB), the switch provides a low insertion loss of 0.50 dB and handles long term evolution (LTE) average power (9 dB peak to average ratio (PAR)) of 40 dBm for full lifetime operation and 43 dBm for single event (

The ADRF6521 is a dual, fully differential, low noise and low distortion variable gain amplifier (VGA). The high spurious-free dynamic range over the gain range makes the ADRF6521 ideal for communication systems with dense constellations, multiple carriers, and nearby interferers. The VGA has a 21 dB attenuation range with a typical voltage gain of 18 dB. The differential input impedance is 100 ?, while the differential output impedance is 16 ?. The ?1 dB gain flatness bandwidth is 2.5 GHz. The output buffers are capable of swinging 1.5 V p-p into 100 ? loads at >55 dBc for second-order and third-order intermodulation distortion (IMD2 and IMD3), and for second and third harmonic distortion (HD2 and HD3) from low frequency to 1 GHz. Variable output dc offset control is accomplished with the OFS1 and OFS2 pins, and the output common-mode can be controlled with the VOCM pin.The ADRF6521 flexibly operates from a single +5 V supply or from a range of dual supplies and consumes a total supply current of 200 mA. When fully disabled, it consumes 25 mA typical. The ADRF6521 is fabricated in an advanced silicon-germanium BiCMOS process and is available in a 20-lead, exposed pad, 3 mm ? 3 mm LFCSP. Performance is specified over the ?40?C to +85?C temperature range.Applications Point-to-point and point-to-multipoint radios Baseband IQ receivers Diversity receivers ADC drivers Instrumentation Medical

The ADRF6650 is a highly integrated downconverter that integrates dual mixers, dual digital switched attenuators, dual digital variable gain amplifiers, a phase-locked loop (PLL), and voltage controlled oscillators (VCOs). In addition, the ADRF6650 integrates two radio frequency (RF) baluns, serial gain control (SGC) controls, and fast enable inputs for time division duplex (TDD) operation.The on-chip RF baluns enable the ADRF6650 to support 50 ? terminated RF inputs. The integrated passive mixer provides a highly linear downconversion for a 200 MHz, sliding, intermediate frequency (IF) window. The ADRF6650 uses broadband square wave limiting local oscillator (LO) amplifiers to achieve an RF bandwidth of 450 MHz to 2700 MHz. Unlike conventional narrow-band sine wave LO amplifier solutions, this amplifier permits the LO to be applied either above or below the RF input over an extremely wide bandwidth.The ADRF6650 offers two alternatives for generating the differential LO input signal: internally via the on-chip fractional-N synthesizer with low phase noise VCOs, or externally via a low phase noise LO signal. The integrated PLL/VCO enables continuous LO coverage from 450 MHz to 2900 MHz. The PLL referenceinput supports a wide frequency range and includes integrated reference dividers before the phase frequency detector (PFD).The ADRF6650 is fabricated using an advanced silicon-germanium (SiGe) bipolar complementary metal-oxide semiconductor(BiCMOS) process. It is available in a 56-lead, RoHS-compliant, 8 mm ? 8 mm, lead frame chip scale package (LFCSP) package with an exposed pad. Performance is specified over the ?40?C to +105?C maximum paddle temperature.Applications Multiband/multistandard cellular base station diversity receivers Wideband radio link diversity downconverters Multimode cellular extenders and picocells

The ADRF6780 is a silicon germanium (SiGe) design, wideband,microwave upconverter optimized for point to point microwaveradio designs operating in the 5.9 GHz to 23.6 GHz frequencyrange.The upconverter offers two modes of frequency translation. The device is capable of direct conversion to radio frequency (RF) from baseband I/Q input signals, as well as single sideband (SSB) upconversion from a real intermediate frequency (IF) input carrier frequency. The baseband inputs are high impedance and are generally terminated off chip with 100 ? differential back terminations. The baseband I/Q input path can be disabled and a modulated real IF signal anywhere from 0.8 GHz to 3.5 GHz can fed into the IF input path and upconverted to 5.9 GHz to 23.6 GHz while suppressing the unwanted sideband by typically better than 25 dBc. The serial port interface (SPI) allows tweaking of the quadrature phase adjustment to allow optimum sideband suppression. In addition, the SPI interface allows powering down the output power detector to reduce power consumption when power monitoring is not necessary.The ADRF6780 upconverter comes in a compact, thermallyenhanced, 5 mm ? 5 mm LFCSP package. The ADRF6780operates over the ?40?C to +85?C temperature range.APPLICATIONS Point to point microwave radios Radar, electronic warfare systems Instrumentation, automatic test equipment (ATE)

The ADRV9002 is a highly integrated RF transceiver that has dual-channel transmitters, dual-channel receivers, integrated synthesizers, and digital signal processing functions.The ADRV9002 is a high performance, highly linear, high dynamic range transceiver designed for performance vs. power consumption system optimization. The device is configurable and ideally suited to demanding, low power, portable and battery powered equipment. The ADRV9002 operates from 30 MHz to 6000 MHz and covers the UHF, VHF, industrial, scientific, and medical (ISM) bands, and cellular frequency bands in narrow-band (kHz) and wideband operation up to 40 MHz. The ADRV9002 is capable of both TDD and FDD operation.The transceiver consists of direct conversion signal paths with state-of-the-art noise figure and linearity. Each complete receiver and transmitter subsystem includes dc offset correction, quadrature error correction (QEC), and programmable digital filters, which eliminate the need for these functions in the digital baseband. In addition, several auxiliary functions, such as auxiliary analog-to-digital converters (ADCs), auxiliary digital-to-analog converters (DACs), and general-purpose inputs/outputs (GPIOs), are integrated to provide additional monitoring and control capability.The fully integrated phase-locked loops (PLLs) provide high performance, low power, fractional-N frequency synthesis for the transmitter, receiver, and clock sections. Careful design and layout techniques provide the isolation required in high performance personal radio applications. All voltage controlled oscillator (VCO) and loop filter components are integrated to minimize the external component count. The local oscillators (LOs) have flexible configuration options and include fast lock modes.The transceiver includes low power sleep and monitor modes to save power and extend the battery life of portable devices while monitoring communications.The fully integrated, low power digital predistortion (DPD) is optimized for both narrow-band and wideband signals and enables linearization of high efficiency power amplifiers.The ADRV9002 core can be powered directly from 1.0 V, 1.3 V, and 1.8 V regulators and is controlled via a standard 4-wire serial port. Other voltage supplies are used to provide proper digital interface levels and to optimize the receiver, transmitter, and auxiliary converter performance.High data rate and low data rate interfaces are supported using configurable CMOS or low voltage differential signaling (LVDS) serial synchronous interface (SSI) choice.The ADRV9002 is packaged in a 12 mm ? 12 mm, 196-ball chip scale package ball grid array (CSP_BGA).APPLICATIONS Mission critical communications Very high frequency (VHF), ultrahigh frequency (UHF), and cellular to 6 GHz Time division duplexing (TDD) and frequency division duplexing (FDD) applications

The receive path consists of two independent, wide bandwidth (BW), direct conversion receivers with state-of-the-art dynamic range. The complete receive subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. RF front-end control and several auxiliary functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) for the power amplifier (PA) are also integrated.In addition to automatic gain control (AGC), the ADRV9008-1 also features flexible external gain control modes, allowing significant flexibility in setting system level gain dynamically.The received signals are digitized with a set of four high dynamic range, continuous time, sigma-delta (?-?) ADCs that provide inherent antialiasing. The combination of the direct conversion architecture, which does not suffer from out of band image mixing, and the lack of aliasing relaxes the requirements of the RF filters compared to traditional intermediate frequency (IF) receivers.The fully integrated phase-locked loop (PLL) provides high per-formance, low power, fractional-N, RF synthesis for the receiver signal paths. An additional synthesizer generates the clocks needed for the converters, digital circuits, and the serial interface. A multi-chip synchronization mechanism synchronizes the phase of the RF local oscillator (LO) and baseband clocks between multiple ADRV9008-1 chips. Precautions are taken to provide the isolation required in high performance base station applications. All voltage controlled oscillators (VCOs) and loop filter components are integrated.The high speed JESD204B interface supports up to 12.288 Gbps lane rates, resulting in two lanes per transmitter and a single lane per receiver in the widest bandwidth mode. The interface also supports interleaved mode for lower bandwidths, reducing the total number of high speed data interface lanes to one. Both fixed and floating point data formats are supported. The floating point format allows internal AGC to be invisible to the demodulator device.The core of the ADRV9008-1 can be powered directly from 1.3 V and 1.8 V regulators and is controlled via a standard 4-wire serial port. Comprehensive power-down modes are included to mini-mize power consumption during normal use. The ADRV9008-1 is packaged in a 12 mm ? 12 mm, 196-ball chip scale ball grid array (CSP_BGA).Applications 3G, 4G, and 5G FDD, macrocell base stations Wide band active antenna systems Massive multiple input, multiple output (MIMO) Phased array radar Electronic warfare Military communications Portable test equipment

The ADRV9026 is a highly integrated, radio frequency (RF) agile transceiver offering four independently controlled transmitters, dedicated observation receiver inputs for monitoring each transmitter channel, four independently controlled receivers, integrated synthesizers, and digital signal processing functions providing a complete transceiver solution. The device provides the performance demanded by cellular infrastructure applications, such as small cell base station radios, macro 3G/4G/5G systems, and massive multiple in/multiple out (MIMO) base stations. The receiver subsystem consists of four independent, wide bandwidth, direct conversion receivers with wide dynamic range. The four independent transmitters use a direct conversion modulator resulting in low noise operation with low power consumption. The device also includes two wide bandwidth, time shared, observation path receivers with two inputs each for monitoring transmitter outputs. The complete transceiver subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. Other auxiliary functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) that provide an array of digital control options are also integrated. To achieve a high level of RF performance, the transceiver includes five fully integrated phase-locked loops (PLLs). Two PLLs provide low noise and low power fractional-N RF synthesis for the transmitter and receiver signal paths. A third fully integrated PLL supports an independent local oscillator (LO) mode for the observation receiver. The fourth PLL generates the clocks needed for the converters and digital circuits, and a fifth PLL provides the clock for the serial data interface. A multichip synchronization mechanism synchronizes the phase of all LOs and baseband clocks between multiple ADRV9026 chips. All voltage controlled oscillators (VCOs) and loop filter components are integrated and adjustable through the digital control interface. The serial data interface consists of four serializer lanes and four deserializer lanes. The interface supports both the JESD204B and JESD204C standards, operating at data rates up to 24.33 Gbps. The interface also supports interleaved mode for lower bandwidths, thus reducing the number of high speed data interface lanes to one. Both fixed and floating-point data formats are supported. The floating-point format allows internal automatic gain control (AGC) to be invisible to the demodulator device. The ADRV9026 is powered directly from 1.0 V, 1.3 V, and 1.8 V regulators and is controlled via a standard serial peripheral interface (SPI) serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9026 is packaged in a 14 mm ? 14 mm, 289-ball chip scale ball grid array (CSP_BGA).Applications 3G/4G/5G TDD and FDD massive MIMO, macro and small cell base stations

The ADTR1107 is a compact, 6 GHz to 18 GHz, front-end IC?with an integrated power amplifier, low noise amplifier (LNA), and a reflective single-pole double-throw (SPDT) switch. These?integrated features make the device ideal for phased array antenna and radar applications. The front-end IC offers 25 dBm of saturated output power (PSAT) and 22?dB small signal gain in?transmit state, and 18 dB small signal gain and 2.5 dB noise figure in receive state. The device has a directional coupler for power detection. The input/outputs (I/Os) are internally matched to 50 ?. The ADTR1107 is supplied in a 5 mm ? 5 mm, 24-terminal, land grid array (LGA) package.Applications Phased array antenna Military radar Weather radar Communication links Electronic warfare

The ADV3002 is a complete HDMI?/DVI link switch featuring equalized transition minimized differential signaling (TMDS) inputs, ideal for systems with long cable runs. The ADV3002 includes bidirectional buffering for the DDC bus and CEC line, with integrated pull-up resistors for the CEC line. Additionally, the ADV3002 includes an EDID replication function that enables one EDID EEPROM to be shared for all four HDMI ports.The ADV3002 is provided in a space-saving, 80-lead LQFP surface-mount Pb-free plastic package and is specified to operate over the 0?C to 85?C temperature range.PRODUCT HIGHLIGHTS Input cable equalizer enables use of long cables at the input. For a 24 AWG cable, the ADV3002 compensates for more than 20m at data rates up to 3 Gbps. Auxiliary multiplexer isolates and buffers the DDC bus and the CEC line, increasing total system capacitance limit. EDID replication eliminates the need for multiple EDID EEPROMs. EDID can be loaded from a single external EEPROM or from a system microcontroller. 5 V power combiner powers the EDID replicator and CEC buffer when local system power is off. Integrated hot plug detect pulse low on channel switch with programmable pulse width or direct manual control.APPLICATIONS Advanced television (HDTV) sets Projectors A/V receivers Set-top boxes

The ADV3219 and ADV3220 are high speed, high slew rate,buffered, 2:1 analog multiplexers. They offer a ?3 dB signalbandwidth greater than 800 MHz and channel switch times ofless than 20 ns with 1% settling. With ?82 dB of crosstalk and?88 dB isolation (at 5 MHz), the ADV3219 and ADV3220 areuseful in many high speed applications. The differential gain ofless than 0.02% and the differential phase of less than 0.02?,together with 0.1 dB flatness beyond 100 MHz while driving a75 ? back terminated load, make the ADV3219 and ADV3220ideal for all types of signal switching. The ADV3219/ADV3220 include an output buffer that can beplaced into a high impedance state to allow multiple outputs tobe connected together for cascading stages without the off channelsloading the output bus. The ADV3219 has a gain of +1, and theADV3220 has a gain of +2; they both operate on ?5 V supplieswhile consuming less than 7.5 mA of idle current.The ADV3219/ADV3220 are available in the 8-lead LFCSPpackage over the extended industrial temperature range of?40?C to +85?C. Applications Routing of high speed signals including ??Video (NTSC, PAL, S, SECAM, YUV, and RGB) ??Compressed video (MPEG, wavelet) ??3-level digital video (HDB3) Data communications Telecommunications

The ADV3221 and?ADV3222 are high speed, high slew rate, buffered 4:1 analog multiplexers. They offer a ?3 dB signal bandwidth greater than 800 MHz and channel switch times of less than 20 ns with 1% settling. With lower than ?58 dB of crosstalk and ?67 dB isolation (at 100 MHz), the ADV3221 and ADV3222 are useful in many high speed applications. The diffe-rential gain error of less than 0.02% and differential phase error of less than 0.02?, together with 0.1 dB gain flatness out to 100 MHz while driving a 75 ? back terminated load, make the ADV3221 and ADV3222 ideal for all types of signal switching.The ADV3221/ADV3222 include an output buffer that can be placed into a high impedance state. This allows multiple outputs to be connected together for cascading stages without the off channels loading the output bus. The ADV3221 has a gain of +1, and the ADV3222 has a gain of +2; they both operate on ?5 V supplies while consuming less than 7.5 mA of idle current. The channel switching is performed via latched control lines, allowing synchronous updating in a multiple ADV3221/ADV3222 envi-ronment.The ADV3221/ADV3222 are offered in a 16-lead SOIC package and are available over the extended industrial temperature range of ?40?C to +85?C.Applications Routing of high speed signals including ? ? Video (NTSC, PAL, S, SECAM, YUV, RGB) ? ? Compressed video (MPEG, wavelet) ? ? 3-level digital video (HDB3) ? ? Data communications ? ? Telecommunications