Microchip’s bPHY Exerciser is a test platform that is used for conformance testing, specifically when conducting a limited physical layer verification. The test platform supports the execution of balanced media physical layer (bPHY) conformance tests in 50 Mbit/s INICnet technology networks. The bPHY Exerciser mainly consists of the bPHY Exerciser hardware and a software that can be used to configure various test scenarios. This document explains you how to setup the test environment, establish required connections and perform specific measurements.

The DIODES DGD05473 and DGD0507A High Frequency, High-Side, Low-Side Gate Drivers in DFN3030-10 are used to optimally drive the gate of MOSFETs. The DGD05473/07A has an integrated bootstrap diode for ease of design and reduced BOM.

This document discusses the case for using piezoelectric buzzers and piezoelectric buzzer drivers

Communicating with ADCs above 500ksps is tough. Adding another variable such as a level translator or isolator to the SPI communication requires more understanding of timing and modifying hardware and firmware. This application note discusses how to achieve the desired dynamic performance with level translators or isolators.

Certified radio modules enabling the radio data transmission in numerous radio frequency bands and radio standards. The radio modules are designed in a way that the mode of operation can be configured via external host micro controller to meet best the requirements of the underlying application. Nevertheless, there are still cases where an adoption or complete change of the firmware is necessary to enable standalone operation, provide new interfaces or simply to optimize the behaviour of the underlying application. Due to the change in firmware the radio certification of the adopted radio module must be verified again. This application note describes in which cases the certification of an adapted radio module can be created on base of the certification of the Würth Elektronik eiSos standard product.

The ubiquity of wireless communications is driving the need for general-purpose RF amplifiers that are applicable to many categories, from 5G systems to radio and antenna applications.

When designing an RF amplifier, the first step is to define some important parameters such as target frequency and gain factor. By selecting the optimal passive components, the transmission characteristics of the amplifier may be enhanced and improved. A well-designed layout that can transmit RF signals and the DC current to power the amplifier stage on a single line without interference or cross-talk further improves RF performance.

A key component for this interference-free operation of the transmission of mixed signals (RF and DC) is the inductor for decoupling the RF and DC supplies. In addition to the usual approach of using a standard inductor, another suitable alternative is to use a multilayer ferrite. To compare and evaluate the ferrite and inductor in this application, an evaluation board of an RF amplifier was realized and measured. This application note also includes circuit design considerations and various recommendations for achieving optimal parameters using two RF amplifier examples.

 Contents:

• Component selection with REDEXPERT
• RF gain block amplifier types in comparison
• Inductors for blocking the RF signal
• DC blocking capacitor selection
• PCB layout considerations
• Measurement setup and results

The first light source for actuating an optoelectronic photosensor was the tungsten filament or incandescent lamp. It was eventually replaced by the GaAs infrared emitting diode which offered longer life, smaller size, less power to operate and less heat generated. The GaAs LED is still the workhorse of the industry and will continue to be used in steadily decreasing numbers for the next few years. It will eventually be replaced by GaAIAs as the industry standard for two major reasons: GaAIAs offer at least twice the power output at the same input current (IF) level and significantly improved coupling efficiency.

The DGD2181M and DGD21814M, High-Side/Low-Side gate drivers are used to optimally drive the gate of MOSFETs or IGBTs. DGD2181M package is SO-8. DGD21814M package is SO-14 with a separate logic ground pin Vss, this can be used when required to separate power ground and logic ground

The Proteus-e is a radio module based on the nRF52 Nordic Semiconductors SoC, which provides various Bluetooth LE and has its focus on low power features. This Application Note shows how easy the "transparent mode" can be used to quickly connect the Proteus-e in order to communicate with a Bluetooth LE connection partner (e.g. a smart device). As second step with more advanced functions, and therefore recommended to be used in applications, the reader is introduced to the Command Mode that is also available to be used on the Proteus-e.

SKEDD is a technology developed by Würth Elektronik with which connectors can be connected to the circuit board directly without soldering. This type of contact offers considerable advantages over soldered connectors.
The REDFIT IDC (insulation displacement connector) is the first series of connectors from Würth Elektronik which comes with SKEDD technology. In the meantime, renowned companies worldwide trust the advantages of SKEDD technology. In this Product Guide you will learn about the advantages of SKEDD and suitable applications for using SKEDD.

This document descirbes implementing the Live Update application on the SAM E54 MCU with the usage of the dual bank Flash.

This manual describes how to use the Renesas Flexible Software Package (FSP) for writing applications for the RZ/T2, RZ/N2 microprocessor series.

This document describes the contents of the Example Project Bundle for the EK-RA6E2 kit. The Example Projects contained within the bundle show how to write code for the various Renesas Flexible Software Package (FSP) modules supported by the EK-RA6E2 kit.

The CoreEDAC IP generates Error Detection And Correction (EDAC) circuitry for both internal (on-chip) and external RAM blocks. The user data is fed to the EDAC encoder, which calculates the parity bits and appends these to the user data, forming a codeword. The codeword is stored into the RAM. During user read, the read codeword is decoded first, which detects and corrects errors (if any), discards parity bits, and outputs the corrected user data word. Scrubbing periodically checks every memory location using the ECC decoder. If a location contains a corrupted word, the decoder detects and corrects the word. The scrubbing circuitry then writes the corrected word back to the same location. To provide normal access to the RAM and prevent decreasing performance, scrubbing is only done during idle periods. The scrubbing circuitry sets a proper write address and write enable signals, writing the corrected codeword back to the RAM. Writeback occurs only upon detecting an error.

This document is intended to guide MPLAB Harmony v2 users on how to develop applications using MPLAB Harmony V3.

This application note walks through the basics of the MAX66250 NFC/RFID device in terms of its use with the associated desktop application. The functionality of the IC is exercised using the development mode of the software, which allows for the configuration of programs to enable the communication, memory, and protection features of the device. Furthermore, the results of these programs can be logged and interpreted in the operator mode of the software.

This application note describes how external compensation works and provides a method to implement it with above-mentioned devices. Through external compensation, the frequency response of buck switching regulators is adjusted to increase or decrease the bandwidth of the system by addition of a simple RC network with a feedback circuit.

When evaluating an amplifier’s performance for a low noise application, both internal and external noise sources must be considered. This application note briefly discusses the fundamentals of both internal and external noise and identifies the tradeoffs associated in selecting the optimal amplifier for low noise design.

This document contains information with respect to the software simulations of the XAUI protocol.

This application note explains how to use the F(1) computation macrocell in the SLG46880/1.

The F(1) Computation Macrocell, also referred to as the F(1) block, is a specialized block within the SLG46880/1’s Asynchronous State Machine (ASM) which allows the designer to trigger sequences of commands upon entering a new state of the ASM.