The AD9515 features a two-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part.There are two independent clock outputs. One output is LVPECL, while the other output can be set to either LVDS or CMOS levels. The LVPECL output operates to 1.6 GHz. The other output operates to 800 MHz in LVDS mode and to 250 MHz in CMOS mode.Each output has a programmable divider that can be set to divide by a selected set of integers ranging from 1 to 32. The phase of one clock output relative to the other clock output can be set by means of a divider phase select function that serves as a coarse timing adjustment.The LVDS/CMOS output features a delay element with three selectable full-scale delay values (1.5 ns, 5 ns, and 10 ns), each with 16 steps of fine adjustment.The AD9515 does not require an external controller for operation or setup. The device is programmed by means of 11 pins (S0 to S10) using 4-level logic. The programming pins are internally biased to ? VS. The VREF pin provides a level of ? VS. VS (3.3 V) and GND (0 V) provide the other two logic levels.The AD9515 is ideally suited for data converter clocking applications where maximum converter performance is achieved by encode signals with subpicosecond jitter.The AD9515 is available in a 32-lead LFCSP and operates from a single 3.3 V supply. The temperature range is ?40?C to +85?C. APPLICATIONS Low jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers High performance instrumentation Broadband infrastructure ATE

The AD9516-1?provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 2.30 GHz to 2.65 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz can be used.The AD9516-1 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements.The AD9516-1 features six LVPECL outputs (in three pairs) and four LVDS outputs (in two pairs). Each LVDS output can be reconfigured as two CMOS outputs. The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz.Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow a range of divisions up to a maximum of 1024.The AD9516-1 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5 V. A separate LVPECL power supply can be from 2.5 V to 3.3 V (nominal).The AD9516-1 is specified for operation over the industrial range of ?40?C to +85?C.APPLICATIONS Low jitter, low phase noise clock distribution 10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4 Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation

The AD9522-21 provides a multioutput clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 2.02 GHz to 2.335 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHz can also be used.The AD9522 serial interface supports both SPI and I2C? ports. An in-package EEPROM can be programmed through the serial interface and store user-defined register settings for power-up and chip reset.The AD9522 features 12 LVDS outputs in four groups. Any of the 800 MHz LVDS outputs can be reconfigured as two 250 MHz CMOS outputs.Each group of outputs has a divider that allows both the divide ratio (from 1 to 32) and the phase (coarse delay) to be set.The AD9522 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. The external VCO can have an operating voltage up to 5.5 V.The AD9522 is specified for operation over the standard industrial range of ?40?C to +85?C.The AD9520-2 is an equivalent part to the AD9522-2 featuring LVPECL/CMOS drivers instead of LVDS/CMOS drivers.1The AD9522 is used throughout this data sheet to refer to all the members of the AD9522 family. However, when AD9522-2 is used, it is referring to that specific member of the AD9522 family.ApplicationsLow jitter, low phase noise clock distributionClock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocolsForward error correction (G.710)Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEsHigh performance wireless transceiversATE and high performance instrumentationBroadband infrastructures

The 10 clock outputs of the AD9542 are synchronized to any one of up to four input references. The digital phase-locked loops (DPLLs) reduce timing jitter associated with the external references. The digitally controlled loop and holdover circuitry continuously generate a low jitter output signal, even when all reference inputs fail.The AD9542 is available in a 48-lead LFCSP (7 mm ? 7 mm) package and operates over the ?40?C to +85?C temperature range.Note that throughout this data sheet, multifunction pins, such as SDO/M5, are referred to either by the entire pin name or by a single function of the pin, for example, M5, when only that function is relevant.Applications SyncE jitter cleanup and synchronization Optical transport networks (OTN), SDH, and macro and small cell base stations OTN mapping/demapping with jitter cleaning Small base station clocking, including baseband and radio Stratum 2, Stratum 3e, and Stratum 3 holdover, jitter cleanup, and phase transient control JESD204B support for analog-to-digital converter (ADC) and digital-to-analog converter (DAC) clocking Cable infrastructures Carrier Ethernet

The AD9543 supports existing and emerging ITU standards for the delivery of frequency, phase, and time of day over service provider packet networks.The 10 clock outputs of the AD9543 are synchronized to any one of up to four input references. The digital phase-locked loops (DPLLs) reduce timing jitter associated with the external references. The digitally controlled loop and holdover circuitry continuously generate a low jitter output signal, even when all reference inputs fail.The AD9543 is available in a 48-lead LFCSP (7 mm ? 7 mm) package and operates over the ?40?C to +85?C temperature range.Note that throughout this data sheet, multifunction pins, such as SDO/M5, are referred to either by the entire pin name or by a single function of the pin, for example, M5, when only that function is relevant.Appliations PTP (IEEE 1588), and SyncE jitter cleanup and synchronization Optical transport networks (OTN), SDH, and macro and small cell base stations OTN mapping/demapping with jitter cleaning Small base station clocking, including baseband and radio Stratum 2, Stratum 3e, and Stratum 3 holdover, jitter cleanup, and phase transient control JESD204B support for analog-to-digital converter (ADC) and digital-to-analog converter (DAC) clocking Cable infrastructures Carrier Ethernet

The AD9552 is a fractional-N phase locked loop (PLL) based clock generator designed specifically to replace high frequency crystal oscillators and resonators. The device employs a sigma-delta (?-?) modulator (SDM) to accommodate fractional frequency synthesis. The user supplies an input reference signal by connecting a single-ended clock signal directly to the REF pin or by connecting a crystal resonator across the XTAL pins.The AD9552 is pin programmable, providing one of 64 standard output frequencies based on one of eight common input frequencies. The device also has a 3-wire SPI interface, enabling the user to program custom input-to-output frequency ratios.The AD9552 relies on an external capacitor to complete the loop filter of the PLL. The output is compatible with LVPECL, LVDS, or single-ended CMOS logic levels, although the AD9552 is implemented in a strictly CMOS process.The AD9552 is specified to operate over the extended industrial temperature range of ?40?C to +85?C.APPLICATIONS Cost effective replacement of high frequency VCXO, OCXO, and SAW resonators Extremely flexible frequency translation with low jitter for SONET/SDH (including FEC) , 10 Gb Ethernet, Fibre Channel, and DRFI/DOCSIS High-definition video frequency translation Wireless infrastructure Test and measurement (including handheld devices)

The AD9553 is a phase-locked loop (PLL) based clock translator designed to address the needs of passive optical networks (PON) and base stations. The device employs an integer-N PLL to accommodate the applicable frequency translation requirements. The user supplies up to two single-ended input reference signals or one differential input reference signal via the REFA and REFB inputs. The device supports holdover applications by allowing the user to connect a 25 MHz crystal resonator to the XTAL input.The AD9553 is pin programmable, providing a matrix of standard input/output frequency translations from a list of 15 possible input frequencies to a list of 52 possible output frequency pairs (OUT1 and OUT2). The device also has a 3-wire SPI interface, enabling the user to program custom input-to-output frequency translations.The AD9553 output is compatible with LVPECL, LVDS, or single-ended CMOS logic levels, although the AD9553 is implemented in a strictly CMOS process.The AD9553 operates over the extended industrial temperature range of ?40?C to +85?C.APPLICATIONS Cost effective replacement of high frequency VCXO, OCXO, and SAW resonators Extremely flexible frequency translation for SONET/SDH, Ethernet, Fibre Channel, DRFI/DOCSIS, and PON/EPON/GPON Wireless infrastructure Test and measurement (including handheld devices)

The AD9571 provides a multioutput clock generator function comprising a dedicated PLL core that is optimized for Ethernet line card applications. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthesizers to maximize network performance. Other applications with demanding phase noise and jitter requirements also benefit from this part.The PLL section consists of a low noise phase frequency detector (PFD), a precision charge pump (CP), a low phase noise voltage controlled oscillator (VCO), and a preprogrammed feedback divider and output divider. By connecting an external crystal or reference clock to the REFCLK pin, frequencies up to 156.25 MHz can be locked to the input reference.Each output divider and feedback divider ratio is preprogrammed for the required output rates. No external loop filter components are required, thus conserving valuable design time and board space.The AD9571 is available in a 40-lead 6 mm ? 6 mm lead frame chip scale package and can be operated from a single 3.3 V supply. The operating temperature range is ?40?C to +85?C.APPLICATIONS Ethernet line cards, switches, and routers SCSI, SATA, and PCI-express PCI support included Low jitter, low phase noise clock generation

The AD9627 is a dual, 12-bit, 80 MSPS/105 MSPS/125 MSPS/150 MSPS analog-to-digital converter (ADC). The AD9627 is designed to support communications applications where low cost, small size and versatility are desired.The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. The AD9627 has several functions that simplify the automatic gain control (AGC) function in the system receiver. The fast detect feature allows fast overrange detection by outputting four bits of input level information with very short latency. In addition, the programmable threshold detector allows monitoring of the incoming signal power, using the four fast detect bits of the ADC with very low latency. If the input signal level exceeds the programmable threshold, the coarse upper threshold indicator goes high. Because this threshold indicator has very low latency, the user can quickly turn down the system gain to avoid an overrange condition. The second AGC-related function is the signal monitor. This block allows the user to monitor the composite magnitude of the incoming signal, which aids in setting the gain to optimize the dynamic range of the overall system. The ADC output data can be routed directly to the two external 12-bit output ports. These outputs can be set from 1.8 V to 3.3 V CMOS or 1.8 V LVDS. Flexible power-down options allow significant power savings, when desired.Programming for setup and control is accomplished using a 3-bit SPI-compatible serial interface.The AD9627 is available in a 64-lead LFCSP and is specified over the industrial temperature range of ?40?C to +85?C.PRODUCT HIGHLIGHTS Integrated dual, 12-bit, 80 MSPS/105 MSPS/125 MSPS/150 MSPS ADC. Fast overrange detect and signal monitor with serial output. Signal monitor block with dedicated serial output mode. Proprietary differential input that maintains excellent SNR performance for input frequencies up to 450 MHz. Operation from a single 1.8 V supply and a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, test modes, and voltage reference mode. Pin compatibility with the AD9640, AD9627-11, and AD9600 for a simple migration from 12 bits to 14 bits, 11 bits, or 10 bits.APPLICATIONS Communications Diversity radio systems Multimode digital receivers (3G) GSM, EDGE, WCDMA, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems General-purpose software radios Broadband data applications

The ADP2381 is a current mode control, synchronous, step-down, dc-to-dc regulator. It integrates a 44 m? power MOSFET and a low-side driver to provide a high efficiency solution. The ADP2381 runs from an input voltage of 4.5 V to 20 V and can deliver 6 A of output current. The output voltage can be adjusted to 0.6 V to 90% of the input voltage. The switching frequency of the ADP2381 can be programmed from 250 kHz to 1.4 MHz or fixed at 290 kHz or 550 kHz. The synchronization function allows the switching frequency to be synchronized to an external clock to minimize system noise.External compensation and an adjustable soft start provide design flexibility. The power-good output provides simple and reliable power sequencing. Additional features include programmable undervoltage lockout (UVLO), overvoltage protection (OVP), overcurrent protection (OCP), and thermal shutdown (TSD).The ADP2381 operates over the ?40?C to +125?C junction temperature range and is available in a 16-lead TSSOP_EP package.APPLICATIONS Communication infrastructure Networking and servers Industrial and instrumentation Healthcare and medical Intermediate power rail conversion DC-to-DC point of load application

The ADP2384 is a synchronous, step-down dc-to-dc regulator with an integrated 44 m?, high-side power MOSFET and an 11.6 m?, synchronous rectifier MOSFET to provide a high efficiency solution in a compact 4 mm ? 4 mm LFCSP package. This device uses a peak current mode, constant frequency pulse-width modulation (PWM) control scheme for excellent stability and transient response. The switching frequency of the ADP2384 can be programmed from 200 kHz to 1.4 MHz. To minimize system noise, the synchronization function allows the switching frequency to be synchronized to an external clock.The ADP2384 requires minimal external components and operates from an input voltage of 4.5 V to 20 V. The output voltage can be adjusted from 0.6 V to 90% of the input voltage and delivers up to 4 A of continuous current. Each IC draws less than 120 ?A current from the input source when it is disabled.This regulator targets high performance applications that require high efficiency and design flexibility. External compensation and an adjustable soft start function provide design flexibility. The power-good output and precision enable input provide simple and reliable power sequencing.Other key features include undervoltage lockout (UVLO), overvoltage protection (OVP), overcurrent protection (OCP), short-circuit protection (SCP), and thermal shutdown (TSD).The ADP2384 operates over the ?40?C to +125?C junction temperature range and is available in a 24-lead, 4 mm ? 4 mm LFCSP package.APPLICATIONS Communications infrastructure Networking and servers Industrial and instrumentation Healthcare and medical Intermediate power rail conversion DC-to-DC point-of-load applications

The ADP2386 is a synchronous step-down, dc-to-dc regulator with an integrated 44 m?, high-side power MOSFET and an 11 m?, synchronous rectifier MOSFET to provide a high efficiency solution in a compact 4 mm ? 4 mm LFCSP package. This device uses a peak current mode, constant frequency pulse-width modulation (PWM) control scheme for excellent stability and transient response. The switching frequency of the ADP2386 can be programmed between 200 kHz to 1.4 MHz. To minimize system noise, the synchronization function allows the switching frequency to be synchronized to an external clock.The ADP2386 requires minimal external components and operates from an input voltage of 4.5 V to 20 V. The output voltage can be adjusted from 0.6 V to 90% of the input voltage and delivers up to 6 A of continuous current. Each IC draws less than 110 ?A current from the input source when it is disabled.This regulator targets high performance applications that require high efficiency and design flexibility. External compensation and an adjustable soft start function provide design flexibility. The power-good output and precision enable input provide simple and reliable power sequencing.Other key features include undervoltage lockout (UVLO), overvoltage protection (OVP), overcurrent protection (OCP), short-circuit protection (SCP) and thermal shutdown (TSD).The ADP2386 operates over the ?40?C to +125?C junction temperature range and is available in a 24-lead, 4 mm ? 4 mm LFCSP package.Applications Communications infrastructure Networking and servers Industrial and instrumentation Healthcare and medical Intermediate power rail conversion DC-to-dc point-of-load applications

The ADP2450 integrates one boost shunt controller with powerdetection, one high efficiency buck regulator, four low offset,low power consumption programmable gain amplifiers (PGAs),one low offset operation amplifier, a fast analog trip circuit, andan actuator driver. The ADP2450 is targeted for low voltagecircuit breakers, such as the molded case circuit breaker(MCCB), and current transformer (CT) powered supplyapplications.The boost output voltage can be up to 36 V and integrates apower detection circuit that prevents the circuit from powerhiccups. The power detection threshold is programmable withresistors.The buck regulator operates over a wide input voltage range of4.5 V to 36 V, and the output voltage can be adjusted down to0.6 V. The buck regulator provides output currents of up to500 mA. The buck regulator works in pulse-width modulation(PWM) mode with a fixed 1.2 MHz switching frequency,providing low output ripple voltage to the system.The output voltage of the buck regulator is monitored by thesupervisory circuit. When the output voltage is below themonitoring threshold, 88% of VFB2 (FB2 regulation voltage), thereset signal is pulled low and can be used to reset themicroprocessor. The monitoring supervisory circuit makes thesystem more reliable.The ADP2450 integrates four low offset, low power consumptionamplifiers. With the programmable gain features, the ADP2450provides accuracy measurement over a wide current input rangebased on the CT turn ratio.A low offset operation amplifier is integrated in the ADP2450for leakage current detection.The ADP2450 also integrates an analog trip circuit, whichprovides fast trip response and enhances system reliability.Additional protection includes buck overcurrent protection(OCP) and system thermal shutdown (TSD).The ADP2450 operates over the ?40?C to +125?C junctiontemperature range and is available either in a 32-lead LFCSP ora 48-lead LQFP packages.Applications Low voltage circuit breaker CT powered supply

The ADP2503 /?ADP2504 are high efficiency, low quiescent current step-up/step-down dc-to-dc converters that can operate at input voltages greater than, less than, or equal to the regulated output voltage. The power switches and synchronous rectifiers are internal to minimize external part count. At high load currents, the ADP2503 / ADP2504 use a current-mode, fixed frequency pulse-width modulation (PWM) control scheme for optimal stability and transient response. To ensure the longest battery life in portable applications, the ADP2503 / ADP2504 have an optional power save mode that reduces the switching frequency under light load conditions. For wireless and other low noise applications where variable frequency power save mode may cause interference, the logic control input sync forces fixed frequency PWM operation under all load conditions.The ADP2503 / ADP2504 can run from input voltages between 2.3 V and 5.5 V, allowing single lithium or lithium polymer cell, multiple alkaline or NiMH cells, PCMCIA, USB, and other standard power sources. The ADP2503 / ADP2504 have fixed output options, or using the adjustable model, the output voltage can be programmed through an external resistor divider. Compensation is internal to minimize the number of external components.During logic-controlled shutdown, the input is disconnected from the output and draws less than 1 ?A from the input source. Operating as boost converters, the ADP2503 / ADP2504 feature a true load disconnect function that isolates the load from the power source. Other key features include undervoltage lockout to prevent deep battery discharge, and soft start to prevent input current overshoot at startup.APPLICATIONS Wireless handsets Digital cameras/portable audio players Miniature hard disk power supplies USB powered devices

The ADP2503?/ ADP2504 are high efficiency, low quiescent current step-up/step-down dc-to-dc converters that can operate at input voltages greater than, less than, or equal to the regulated output voltage. The power switches and synchronous rectifiers are internal to minimize external device count. At high load currents, the ADP2503 / ADP2504 use a current-mode, fixed frequency pulse-width modulation (PWM) control scheme for optimal stability and transient response. To ensure the longest battery life in portable applications, the ADP2503 / ADP2504 have an optional power save mode that reduces the switching frequency under light load conditions. For wireless and other low noise applications where variable frequency power save mode may cause interference, the logic control input sync forces fixed frequency PWM operation under all load conditions.?The ADP2503 / ADP2504 can run from input voltages between 2.3 V and 5.5 V, allowing single lithium or lithium polymer cell, multiple alkaline or NiMH cells, PCMCIA, USB, and other standard power sources. The ADP2503 / ADP2504 have fixed output options, or using the adjustable model, the output voltage can be programmed through an external resistor divider. Compensation is internal to minimize the number of external components.During logic-controlled shutdown, the input is disconnected from the output and draws less than 1 ?A from the input source. Operating as boost converters, the ADP2503 / ADP2504 feature a true load disconnect function that isolates the load from the power source. Other key features include undervoltage lockout to prevent deep battery discharge, and soft start to prevent input current overshoot at startup.APPLICATIONSWireless handsetsDigital cameras/portable audio playersMiniature hard disk power suppliesUSB powered devices?

The ADP5063 charger is fully compliant with USB 3.0 and the USB Battery Charging 1.2 Compliance Plan Specification, and enables charging via the mini USB VBUS pin from a wall charger, car charger, or USB host port.The ADP5063 operates from a 4 V to 6.7 V input voltage range but is tolerant of voltages up to 20 V, thereby alleviating concerns about USB bus spikes during disconnection or connection scenarios.The ADP5063 features an internal field effect transistor (FET) between the linear charger output and the battery. This permits battery isolation and, therefore, system powering under a dead battery or no battery scenario, which allows immediate system function upon connection to a USB power supply.Based on the type of USB source, which is detected by an external USB detection chip, the ADP5063 can be set to apply the correct current limit for optimal charging and USB compliance.The ADP5063 has three factory-programmable digital input/out-put pins that provide maximum flexibility for different systems. These digital input/output pins permit a combination of features, such as input current limits, charging enable and disable, charging current limits, and a dedicated interrupt output pin.APPLICATIONS Single cell LiFePO4 portable equipment Portable medical devices Portable instrumentation devices Portable consumer devices

The ADP5073 is a high performance dc-to-dc inverting regulator used to generate negative supply rails.The input voltage range of 2.85 V to 15 V supports a wide variety of applications. The integrated main switch enables the generation of an adjustable negative output voltage down to 39 V below the input voltage.The ADP5073 operates at a pin selected 1.2 MHz/2.4 MHz switching frequency. The ADP5073 can synchronize with an external oscillator from 1.0 MHz to 2.6 MHz to ease noise filtering in sensitive applications. The regulator implements programmable slew rate control circuitry for the MOSFET driver stage to reduce electromagnetic interference (EMI).The ADP5073 includes a fixed internal or resistor programmable soft start timer to prevent inrush current at power-up. During shutdown, the regulator completely disconnects the load from the input supply to provide a true shutdown. A power-good pin is available to indicate the output is stable.Other key safety features in the ADP5073 include overcurrent protection (OCP), overvoltage protection (OVP), thermal shutdown (TSD), and input undervoltage lockout (UVLO).The ADP5073 is available in a 16-lead LFCSP and is rated for a ?40?C to +125?C operating junction temperature range.Applications Bipolar amplifiers, ADCs, digital-to-analog converters (DACs), and multiplexers High speed converters Radio frequency (RF) power amplifier (PA) bias Optical modules

The ADP5074 is a high performance dc-to-dc inverting regulator used to generate negative supply rails.The input voltage range of 2.85 V to 15 V supports a wide variety of applications. The integrated main switch enables the generation of an adjustable negative output voltage down to 39 V below the input voltage.The ADP5074 operates at a pin selected 1.2 MHz/2.4 MHz switching frequency. The ADP5074 can synchronize with an external oscillator from 1.0 MHz to 2.6 MHz to ease noise filtering in sensitive applications. The regulator implements programmable slew rate control circuitry for the MOSFET driver stage to reduce electromagnetic interference (EMI).The ADP5074 includes a fixed internal or resistor programmable soft start timer to prevent inrush current at power-up. During shutdown, the regulator completely disconnects the load from the input supply to provide a true shutdown. A power good pin is available to indicate the output is stable.Other key safety features in the ADP5074 include overcurrent protection (OCP), overvoltage protection (OVP), thermal shutdown (TSD), and input undervoltage lockout (UVLO).The ADP5074 is available in a 16-lead LFCSP and is rated for a ?40?C to +125?C operating junction temperature range.Applications Bipolar amplifiers, ADCs, digital-to-analog converters (DACs), and multiplexers High speed converters Radio frequency (RF) power amplifier (PA) bias Optical modules

The ADP5133 combines two high performance buck regulators in a tiny, 16-ball, 2 mm ? 2 mm WLCSP to meet demanding performance and board space requirements.The high switching frequency of the buck regulators enables tiny multilayer external components and minimizes the board space. When the MODE pin is set high, the buck regulators operate in forced PWM mode. When the MODE pin is set low and the buck regulators operate in PWM mode, the load current is above a predefined threshold. When the load current falls below a predefined threshold, the regulators operate in power save mode (PSM), improving the light load efficiency.The two bucks operate out of phase to reduce the input capacitor requirement and noise.The regulators in the ADP5133 are activated through dedicated enable pins. The output voltages can be externally set through a resistor feedback network.Applications Power for processors, ASICs, FPGAs, and RF chipsets Portable instrumentation and medical devices Space constrained devices

The ADP5360 combines one high performance linear charger?for a single lithium-ion (Li-Ion)/lithium-polymer (Li-Poly)?battery with a programmable, ultralow quiescent current fuel?gauge and battery protection circuit, one ultralow quiescent?buck, one buck boost switching regulator, and a supervisory?circuit that can monitor output voltage.The ADP5360 charger operates at up to 6.8 V to prevent USB?bus spiking during disconnect or connect scenarios.The ADP5360 features an internal isolation field effect transistor?(FET) between the linear charger output and the battery node.?The full battery protection features are activated when the device is?in the battery overcharge and overdischarge fault conditions.The ADP5360 fuel gauge uses a voltage-based algorithm with?an adaptive filter limitation solution. The fuel gauge reports?real-time battery state of charge (SOC) for the rechargeable?Li-Ion battery with ultralow quiescent current.The ADP5360 buck regulator operates at 1.0 MHz switching?frequency in forced pulse-width modulation (FPWM) mode.?In hysteresis mode, the regulator achieves excellent efficiency at?a low output power.The ADP5360 buck boost regulator only operates in hysteresis?mode and outputs a voltage less than or greater than the battery?voltage.The ADP5360 supervisory circuits monitor the regulator output?voltage and provide a power-on reset signal to the system. A?watchdog timer and an external pushbutton can reset the?microprocessor.The I2C-compatible interface enables the programmability of all?battery charging parameters, the protection threshold, the buck?output voltage, and the status bit readback.The ADP5360 operates over the ?40?C to +85?C junction?temperature range and is available in a 32-ball, 2.56 mm נ2.56 mm wafer level chip scale package (WLCSP).Applications Rechargeable Li-Ion/Li-Poly battery-powered devices Portable consumer devices Portable medical devices Wearable devices