The?AD8494/AD8495/AD8496/AD8497?are precision instrumentation amplifiers with thermocouple cold junction compensators on an integrated circuit. They produce a high level (5 mV/?C) output directly from a thermocouple signal by combining an ice point reference with a precalibrated amplifier. They can be used as standalone thermometers or as switched output setpoint controllers using either a fixed or remote setpoint control.The AD8494/AD8495/AD8496/AD8497 can be powered from a single-ended supply (less than 3 V) and can measure temperatures below 0?C by offsetting the reference input. To minimize self-heating, an unloaded AD849x typically operates with a total supply current of 180 ?A, but it is also capable of delivering in excess of ?5 mA to a load.The AD8494 and AD8496 are precalibrated by laser wafer trimming to match the characteristics of J type (iron-constantan) thermocouples; the AD8495 and AD8497 are laser trimmed to match the characteristics of K type (chromel-alumel) thermo-couples. See Table 1 on the data sheet for the optimized ambient temperature range of each part.The AD8494/AD8495/AD8496/AD8497 allow a wide variety of supply voltages. With a 5 V single supply, the 5 mV/?C output allows the devices to cover nearly 1000 degrees of a thermo-couple?s temperature range.The AD8494/AD8495/AD8496/AD8497 work with 3 V supplies, allowing them to interface directly to lower supply ADCs. They can also work with supplies as large as 36 V in industrial systems that require a wide common-mode input range.Product Highlights Complete, precision laser wafer trimmed thermocouple signal conditioning system in a single IC package. Flexible pinout provides for operation as a setpoint controller or as a standalone Celsius thermometer. Rugged inputs withstand 4 kV ESD and provide over-voltage protection (OVP) up to VS ? 25 V. Differential inputs reject common-mode noise on the thermocouple leads. Reference pin voltage can be offset to measure 0?C on single supplies. Available in a small, 8-lead MSOP that is fully RoHS compliant. Applications J type thermocouple temperature measurement Setpoint controller Celsius thermometer Universal cold junction compensator White goods (oven, stove top) temperature measurements Exhaust gas temperature sensing Catalytic converter temperature sensing div#landing_page_sec ul { padding:0 0 15px 10px; margin:0px; } div#landing_page_sec li { padding:3px 0 2px 20px; margin:0px; list-style:none; background:url(/static/imported-files/embedded_html/images/li_img.gif) no-repeat 7px 9px; display:block; color:#000000; font-family: Arial, Helvetica, sans-serif; }

The AD8556 is a zero-drift, sensor signal amplifier withdigitally programmable gain and output offset. Designed toeasily and accurately convert variable pressure sensor andstrain bridge outputsto a well-defined output voltage range,the AD8556 accurately amplifies many other differential orsingle-ended sensor outputs. The AD8556 uses the ADIpatented low noise auto-zero and DigiTrim? technologies tocreate an incredibly accurate and flexible signal processingsolution in a very compact footprint.Gain is digitally programmable in a wide range from 70 to1,280 through a serial data interface. Gain adjustment canbe fully simulated in-circuit and then permanently programmedwith reliable polyfuse technology. Output offsetvoltage is also digitally programmable and is ratiometric to thesupply voltage. AD8556 also features internal EMI filters on theVNEG, VPOS, FILT and VCLAMP pins.In addition to extremely low input offset voltage, low inputoffset voltage drift, and very high dc and ac CMRR, the AD8556 also includes a pull-up current source at the input pinsand a pull-down current source at the VCLAMP pin. Thisallows open wire and shorted wire fault detection. A low-passfilter function is implemented via a single low cost externalcapacitor. Output clamping set via an external reference voltageallows the AD8556 to drive lower voltage ADCs safely andaccurately.When used in conjunction with an ADC referenced to the samesupply, the system accuracy becomes immune to normal supplyvoltage variations. Output offset voltage can be adjusted with aresolution of better than 0.4% of the difference between VDDand VSS. A lockout trim after gain and offset adjustmentfurther ensures field reliability.The AD8556 is fully specified from ?40?C to +140?C.Operating from single-supply voltages of 2.7 V to 5.5 V, theAD8556 is offered in the 8-lead SOIC_N, and 4 mm ? 4 mm16-lead LFCSP_VQ.ApplicationsAutomotive SensorsPressure and Position SensorsPrecision Current SensingStrain Gages

The AD9083 is a 16-channel, 125 MHz bandwidth, continuous time ?-? (CTSD) ADC. The device features an on-chip, programmable, single-pole antialiasing filter and termination resistor that is designed for low power, small size, and ease of use. The 16 ADC cores features a first-order, CTSD modulator architecture with integrated, background nonlinearity correction logic and self cancelling dither. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The analog input and clock signals are differential inputs. Each ADC has a signal processing tile to filter out of band shaped noise from the ?-? ADC and reduce the sample rate. Each tile contains a cascaded integrator comb (CIC) filter, a quadrature digital downconverter (DDC) with multiple finite input response (FIR) decimation filters (decimate by J block), or up to three quadrature DDC channels with averaging decimation filters for data gating applications. Users can configure the Subclass 1 JESD204B based, high speed serialized output in a variety of lane configurations (up to four), depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF?, TRIG?, and SYNCINB? input pins. The AD9083 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V capable 3-wire serial port interface (SPI). The AD9083 is available in a Pb-free, 100-ball CSP_BGA and is specified over the ?40?C to +85?C industrial temperature range.This product is protected by a US patent.APPLICATIONS Millimeter wave imaging Electronic beam forming and phased arrays Multichannel wideband receivers Electronic support measuresPRODUCT HIGHLIGHTS Continuous time, ?-? analog-to-digital converters (ADCs) support signal bandwidths of up to 125 MHz with low power and minimal filtering. Integrated digital processing blocks reduce data payload and lower overall system cost. Configurable JESD204B interface reduces printed circuit board (PCB) complexity. Flexible power-down options. SPI interface controls various product features and functions to meet specific system requirements. Small, 9 mm ? 9 mm, 100-ball CSP_BGA package, simple interface, and integrated digital processing save PCB space.

The AD9125 is a dual, 16-bit, high dynamic range TxDAC+? digital-to-analog converter (DAC) that provides a sample rate of 1000 MSPS, permitting a multicarrier generation up to the Nyquist frequency. It includes features optimized for direct conversion transmit applications, including complex digital modulation, and gain and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators, such as the ADL537x F-MOD series from Analog Devices, Inc. A 4-wire serial port interface allows programming/readback of many internal parameters. Full-scale output current can be programmed over a range of 8.7 mA to 31.7 mA. The AD9125 comes in a 72-lead LFCSP.PRODUCT HIGHLIGHTS Ultralow noise and intermodulation distortion (IMD) enable high quality synthesis of wideband signals from baseband to high intermediate frequencies. A proprietary DAC output switching technique enhances dynamic performance. The current outputs are easily configured for various single-ended or differential circuit topologies. Flexible CMOS digital interface allows the standard 32-wire bus to be reduced to a 16-wire bus.APPLICATIONS Wireless infrastructure W-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM, LTE Digital high or low IF synthesis Transmit diversity Wideband communications: LMDS/MMDS, point-to-point Cable modem termination systems

The AD9142A is a dual, 16-bit, high dynamic range digital-to-analog converter (DAC) that provides a sample rate of 1600 MSPS, permitting a multicarrier generation up to the Nyquist frequency. The AD9142A TxDAC+? includes features optimized for direct conversion transmit applications, including complex digital modulation, input signal power detection, and gain, phase, and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators, such as the ADL537x F-MOD series and the ADRF670x series from Analog Devices, Inc. A 3-wire serial port interface provides for the programming/readback of many internal parameters. Full-scale output current can be programmed over a range of 9 mA to 33 mA. The AD9142A is available in a 72-lead LFCSP.PRODUCT HIGHLIGHTS Wide signal bandwidth (BW) enables emerging wideband and multiband wireless applications. Advanced low spurious and distortion design techniques provide high quality synthesis of wideband signals from baseband to high intermediate frequencies. Very small inherent latency variation simplifies both software and hardware design in the system. It allows easy multichip synchronization for most applications. New low power architecture improves power efficiency (mW/MHz/channel) by 30%. Input signal power and FIFO error detection simplify designs for downstream analog circuitry protection. Programmable transmit enable function allows easy design balance between power consumption and wakeup time.APPLICATIONS Wireless communications: 3G/4G and MC-GSM base stations, wideband repeaters, software defined radios Wideband communications: point-to-point, LMDS/MMDS Transmit diversity/MIMO Instrumentation Automated test equipment

The AD9142A is a dual, 16-bit, high dynamic range digital-to-analog converter (DAC) that provides a sample rate of 1600 MSPS, permitting a multicarrier generation up to the Nyquist frequency. The AD9142A TxDAC+? includes features optimized for direct conversion transmit applications, including complex digital modulation, input signal power detection, and gain, phase, and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators, such as the ADL537x F-MOD series and the ADRF670x series from Analog Devices, Inc. A 3-wire serial port interface provides for the programming/readback of many internal parameters. Full-scale output current can be programmed over a range of 9 mA to 33 mA. The AD9142A is available in a 72-lead LFCSP.PRODUCT HIGHLIGHTS Wide signal bandwidth (BW) enables emerging wideband and multiband wireless applications. Advanced low spurious and distortion design techniques provide high quality synthesis of wideband signals from baseband to high intermediate frequencies. Very small inherent latency variation simplifies both software and hardware design in the system. It allows easy multichip synchronization for most applications. New low power architecture improves power efficiency (mW/MHz/channel) by 30%. Input signal power and FIFO error detection simplify designs for downstream analog circuitry protection. Programmable transmit enable function allows easy design balance between power consumption and wakeup time.APPLICATIONS Wireless communications: 3G/4G and MC-GSM base stations, wideband repeaters, software defined radios Wideband communications: point-to-point, LMDS/MMDS Transmit diversity/MIMO Instrumentation Automated test equipment

The AD9144 is a quad, 16-bit, high dynamic range digital-to-analog converter (DAC) that provides a maximum sample rate of 2.8 GSPS, permitting a multicarrier generation up to the Nyquist frequency. The DAC outputs are optimized to interface seamlessly with the ADRF6720 analog quadrature modulator (AQM) from Analog Devices, Inc. An optional 3-wire or 4-wire serial port interface (SPI) provides for programming/readback of many internal parameters. Full-scale output current can be programmed over a typical range of 13.9 mA to 27.0 mA. The AD9144 is available in an 88-lead LFCSP.Product Highlights Greater than 1 GHz, ultrawide complex signal bandwidth enables emerging wideband and multiband wireless applications. Advanced low spurious and distortion design techniques provide high quality synthesis of wideband signals from baseband to high intermediate frequencies. JESD204B Subclass 1 support simplifies multichip synchronization in software and hardware design. Fewer pins for data interface width with a serializer/deserializer (SERDES) JESD204B eight-lane interface. Programmable transmit enable function allows easy design balance between power consumption and wake-up time. Small package size with 12 mm ? 12 mm footprint.Applications Wireless communications 3G/4G W-CDMA base stations Wideband repeaters Software defined radios Wideband communications Point-to-point Local multipoint distribution service (LMDS) and multichannel multipoint distribution service (MMDS) Transmit diversity, multiple input/multiple output (MIMO) Instrumentation Automated test equipment

The AD9152 is a dual, 16-bit, high dynamic range digital-to-analog converter (DAC) that provides a maximum sample rate of 2.25 GSPS, permitting a multicarrier generation up to the Nyquist frequency. The DAC outputs are optimized to interface seamlessly with the ADRF6720 analog quadrature modulator (AQM)from Analog Devices, Inc. An optional 3-wire or 4-wire serial port interface (SPI) provides for programming/readback of many internal parameters. The full-scale output current can be programmed over a range of 4 mA to 20 mA. The AD9152 isavailable in a 56-lead LFCSP. The AD9152 is a member of theTxDAC+? family.Product Highlights Ultrawide signal bandwidth enables emerging wideband and multiband wireless applications. Advanced low spurious and distortion design techniques provide high quality synthesis of wideband signals from baseband to high intermediate frequencies. JESD204B Subclass 1 support simplifies multichip synchronization in software and hardware design. Fewer pins for data interface width with the serializer/deserializer (SERDES) JESD204B four-lane interface. Programmable transmit enable function allows easy design balance between power consumption and wake-up time. Small package size with an 8 mm ? 8 mm footprint. ?Applications Wireless communications Multicarrier LTE and GSM base stations Wideband repeaters Software defined radios Wideband communications Point to point microwave radios LMDS/MMDS Transmit diversity, multiple input/multiple output (MIMO) Instrumentation Automated test equipment

The AD9154 is a quad, 16-bit, high dynamic range digital-to-analog converter (DAC) that provides a maximum sample rate of 2.4 GSPS, permitting multicarrier generation up to the Nyquist frequency in baseband mode. The AD9154 includes features optimized for direct conversion transmit applications including complex digital modulation, input signal power detection, and gain, phase, and offset compensation. The DAC outputs are?optimized to interface seamlessly with the ADRF6720-27 radio?frequency quadrature modulator (AQM) from Analog Devices,?Inc. In mix mode, the AD9154 DAC can reconstruct carriers in the second and third Nyquist Zones. A serial port interface (SPI)?provides the programming/readback of internal parameters. The full-scale output current can be programmed over a range of 4 mA to 20 mA. The AD9154 is available in two different?88-lead LFCSP packages.PRODUCT HIGHLIGHTS? Ultrawide signal bandwidth enables emerging wideband and multiband wireless applications. Advanced low spurious and distortion design techniques provide high quality synthesis of wideband signals from baseband to high intermediate frequencies. JESD204B Subclass 1 support simplifies multichip synchronization. Small package size with a 12 mm ? 12 mm footprint.APPLICATIONS Wireless communications Multicarrier LTE and GSM base stations Wideband repeaters Software defined radios Wideband communications Point to point microwave radio Transmit diversity, multiple input/multiple output (MIMO) Instrumentation Automated test equipment

The AD91661 is a high performance, wideband, on-chip vector signal generator composed of a high speed JESD204B serializer/deserializer (SERDES) interface, a flexible 16-bit digital datapath, a inphase/quadrature (I/Q) digital-to-analog converter (DAC) core, and an integrated differential to single-ended outputbuffer amplifier, matched to a 50 ? load up to 10 GHz.The DAC core is based on a quad-switch architecture, which is configurable to increase the effective DAC core update rate of up to 12.8 GSPS from a 6.4 GHz DAC sampling clock, with an analog output bandwidth of true dc to 9.0 GHz, typically. The digital datapath includes multiple interpolation filter stages, a direct digital synthesizer (DDS) block with multiple numerically controlled oscillators (NCOs) supporting fast frequency hopping (FFH), and additional FIR85 and inverse sinc filter stages to allow flexible spectrum planning.The differential to single-ended buffer eliminates the need for a wideband balun, and supports the full analog output bandwidth of the DAC core. DC coupling the output allows baseband waveform generation without the need for external bias tees or similar circuitry, which makes the AD9166 uniquely suited for the mostdemanding high speed ultrawideband RF transmit applications. The various filter stages enable the AD9166 to be configured for lower data rates, while maintaining higher DAC clock rates to ease the filtering requirements and reduce the overall system size, weight, and power.The data interface receiver consists of up to eight JESD204B SERDES lanes, each capable of carrying up to 12.5 Gbps. To enable maximum flexibility, the receiver is fully configurable according to the data rate, number of SERDES lanes, and lane mapping required by the JESD204B transmitter.In 2? nonreturn-to-zero (NRZ) mode of operation (with FIR85 enabled), the AD9166 can reconstruct RF carriers from true dc to the edge of the third Nyquist zone, or an analog bandwidth of true dc up to 9 GHz.In mix mode, the AD9166 can reconstruct RF carriers in the second and third Nyquist zones while consuming lower power and maintaining a performance comparable to 2? NRZ mode.In baseband modes, such as return-to-zero (RZ) and 1? NRZ, the AD9166 is ideal to reconstruct RF carriers from true dc to the edge of the first Nyquist zone while consuming lower power compared to 2? NRZ mode.The quadrature DDS block can be configured as a digital upconverter to upconvert I/Q data samples to the desired location across the spectrum, in all three Nyquist zones.The DDS also consists of a bank of 32 numerically controlled oscillators (NCOs), each with its own 32-bit phase accumulator. When combined with a 100 MHz serial peripheral interface (SPI), the DDS allows a phase coherent FFH, with a phase settling time as low as 300 ns.The AD9166 is configured using a common SPI interface that monitors the status of all registers. The AD9166 is offered in a 324-ball, 15 mm ? 15 mm, 0.8 mm pitch BGA_ED package.Product Highlights High dynamic range and signal reconstruction bandwidth supports RF signal synthesis of up to 9 GHz. Fully supports zero IF and other dc-coupled applications. Up to an eight-lane JESD204B SERDES interface, with various features to allow flexibility when interfacing to a JESD204B transmitter.Applications Instrumentation: automated test equipment, electronic test and measurement, arbitrary waveform generators Electronic warfare: radars, jammers Broadband communications systems Local oscillator drivers1 Protected by U.S. Patents 6,842,132 and 7,796,971.

The AD9172 is a high performance, dual, 16-bit digital-to-analog converter (DAC) that supports DAC sample rates to 12.6 GSPS. The device features an 8-lane, 15 Gbps JESD204B data input port, a high performance, on-chip DAC clock multiplier, and digital signal processing capabilities targeted at single-band and multiband direct to radio frequency (RF) wireless applications.The AD9172 features three complex data input channels per RF DAC that are bypassable. Each data input channel includes a configurable gain stage, an interpolation filter, and a channel numerically controlled oscillator (NCO) for flexible, multiband frequency planning. The device supports up to a 1.5 GSPS complex data rate per input channel and is capable of aggregating multiple complex input data streams up to a maximum complex data rate of 1.5 GSPS. Additionally, the AD9172 supports ultrawide bandwidth modes bypassing the channelizers to provide maximum data rates of up to 3.08 GSPS (with 16-bit resolution) and 4.1 GSPS (with 12-bit resolution).The AD9172 is available in a 144-ball BGA_ED package.PRODUCT HIGHLIGHTS Supports single-band and multiband wireless applications with three bypassable complex data input channels per RF DAC at a maximum complex input data rate of 1.5 GSPS. One independent NCO per input channel. Ultrawide bandwidth channel bypass modes supporting up to 3 GSPS data rates with 16-bit resolution and 4 GSPS with 12-bit resolution. Low power dual converter decreases the amount of power consumption needed in high bandwidth and multichannel applications.APPLICATIONS Wireless communications infrastructure Multiband base station radios Microwave/E-band backhaul systems Instrumentation, automatic test equipment (ATE) Radars and jammers

The AD9211 is a 10-bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. The product operates at up to a 300 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a track-and-hold (T/H) and voltage reference, are included on the chip to provide a complete signal conversion solution.The ADC requires a 1.8 V analog voltage supply and a differential clock for full performance operation. The digital outputs are LVDS (ANSI-644) compatible and support either twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing.Fabricated on an advanced CMOS process, the AD9211 is available in a 56-lead LFCSP, specified over the industrial temperature range (?40?C to +85?C).PRODUCT HIGHLIGHTS High Performance?Maintains 60.1 dBFS SNR @ 300 MSPS with a 70 MHz input. Low Power?Consumes only 410 mW @ 300 MSPS. Ease of Use?LVDS output data and output clock signal allow interface to current FPGA technology. The on-chip reference and sample-and-hold provide flexibility in system design. Use of a single 1.8 V supply simplifies system power supply design. Serial Port Control?Standard serial port interface supports various product functions, such as data formatting, disabling the clock duty cycle stabilizer, power-down, gain adjust, and output test pattern generation. Pin-Compatible Family?12-bit pin-compatible family offered as AD9230.APPLICATIONS Wireless and wired broadband communications Cable reverse path Communications test equipment Radar and satellite subsystems Power amplifier linearization

The AD9234 is a dual, 12-bit, 1 GSPS/500 MSPS ADC. The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed for sampling wide bandwidth analog signals. The AD9234 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth buffered inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. Each ADC data output is internally connected to an optional decimate-by-2 block. The AD9234 has several functions that simplify the automatic gain control (AGC) function in a communications receiver.?The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. In addition to the fast detect outputs, the AD9234 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC.Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, or four-lane configurations, depending on the acceptable lane rate of the receiving logic device and the sampling rate of the ADC. Multiple device synchronization is supported through the SYSREF? and SYNCINB? input pins.The AD9234 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V to 3.3 V capable 3-wire SPI.The AD9234 is available in a Pb-free, 64-lead LFCSP and is specified over the ?40?C to +85?C industrial temperature range. This product is protected by a U.S. patent.Product Highlights Low power consumption analog core, 12-bit, 1.0 GSPS dual analog-to-digital converter (ADC) with 1.5 W per channel. Wide full power bandwidth supports IF sampling of signals up to 2 GHz. Buffered inputs with programmable input termination eases filter design and implementation. Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements. Programmable fast overrange detection. 9 mm ? 9 mm 64-lead LFCSP. Pin compatible with the AD9680 14-bit, 1 GSPS dual ADC.Applications Communications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE Point-to-point radio systems Digital predistortion observation path General-purpose software radios Ultrawideband satellite receiver Instrumentation (spectrum analyzers, network analyzers, integrated RF test solutions) Digital oscilloscopes High speed data acquisition systems DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers

The AD9249 is a 16-channel, 14-bit, 65 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit that is designed for low cost, low power, small size, and ease of use. The device operates at a conversion rate of up to 65 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.The ADC requires a single 1.8 V power supply and an LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.The AD9249 automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. Data clock outputs (DCO?1, DCO?2) for capturing data on the output and frame clock outputs (FCO?1, FCO?2) for signaling a new output byte are provided. Individual channel power-down is supported, and the device typically consumes less than 2 mW when all channels are disabled. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation.The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).The AD9249 is available in an RoHS-compliant, 144-ball CSP-BGA. It is specified over the industrial temperature range of ?40?C to +85?C. This product is protected by a U.S. patent.PRODUCT HIGHLIGHTS Small Footprint. Sixteen ADCs are contained in a small, 10 mm ? 10 mm package. Low Power of 35 mW/Channel at 20 MSPS with scalable power options. Ease of Use. Data clock outputs (DCO?1, DCO?2) operate at frequencies of up to 455 MHz and support double data rate (DDR) operation. User Flexibility. SPI control offers a wide range of flexible features to meet specific system requirements.APPLICATIONS Medical imaging Communications receivers Multichannel data acquisition

The AD9255 is a 14-bit, 125 MSPS analog-to-digital converter (ADC). The AD9255 is designed to support communications applications where high performance combined with low cost, small size, and versatility is desired.The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic to provide 14-bit accuracy at 125 MSPS data rates and guarantees no missing codes over the full operating temperature range.The ADC features a wide bandwidth differential sample-and-hold analog input amplifier supporting a variety of user-selectable input ranges. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling single-channel inputs at frequencies well beyond the Nyquist rate. Combined with power and cost savings over previously available ADCs, the AD9255 is suitable for applications in communications, instrumentation, and medical imaging.A differential clock input controls all internal conversion cycles. A duty cycle stabilizer provides the means to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance over a wide range of input clock duty cycles. An integrated voltage reference eases design considerations.The ADC output data format is either parallel 1.8 V CMOS or LVDS (DDR). A data output clock is provided to ensure proper latch timing with receiving logic.Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface. Flexible power-down options allow significant power savings, when desired. An optional on-chip dither function is available to improve SFDR performance with low power analog input signals.The AD9255 is available in a Pb-free, 48-lead LFCSP and is specified over the industrial temperature range of ?40?C to +85?C.PRODUCT HIGHLIGHTS On-chip dither option for improved SFDR performance with low power analog input. Proprietary differential input that maintains excellent SNR performance for input frequencies up to 300 MHz. Operation from a single 1.8 V supply and a separate digital output driver supply accommodating 1.8 V CMOS or LVDS outputs. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, test modes, and voltage reference mode. ?Pin compatibility with the AD9265, allowing a simple migration up to 16 bits.Applications Communications Multimode digital receivers (3G) GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, and TD-SCDMA Smart antenna systems General-purpose software radios Broadband data applications Ultrasound equipment

The AD9286 is an 8-bit, monolithic sampling, analog-to-digital converter (ADC) that supports interleaved operation and is optimized for low cost, low power, and ease of use. Each ADC operates at up to a 250 MSPS conversion rate with outstanding dynamic performance.The AD9286 takes a single sample clock and, with an on-chip clock divider, time interleaves the two ADC cores (each running at one-half the clock frequency) to achieve the rated 500 MSPS. By using the SPI, the user can accurately adjust the timing of the sampling edge per ADC to minimize the image spur energy.The ADC requires a single 1.8 V supply and an encode clock for full performance operation. No external reference components are required for many applications. The digital outputs are LVDS compatible.The AD9286 is available in a Pb-free, 48-lead LFCSP that is specified over the industrial temperature range of ?40?C to +85?C. PRODUCT HIGHLIGHTS Integrated 8-bit, 500 MSPS ADC. Single 1.8 V supply operation with LVDS outputs. Power-down option controlled via a pin-programmable setting.?APPLICATIONS Battery-powered instruments Handheld scope meters Low cost digital oscilloscopes OTS: video over fiber

The AD9512 provides a multi-output clock distribution function for input signals up to 1.6 GHz. The design emphasizes low jitter and low phase noise in order to maximize data converter clocking performance. Three independent LVPECL and two LVDS clock outputs operate to 1.2 GHz and 800 MHz respectively. Optional CMOS clock outputs available to 250 MHz. Each output has a programmable divider, which may be bypassed or set to divide by any integer up to 32.Each divider allows the user to change the phase of one clock output relative to another clock output. This phase select functions as a coarse timing adjustment. One output also features a programmable delay element with a user-selected, fullscale range to 10 ns. This fine tuning delay block is programmed with a 5-bit word, which gives the user 32 possible delays from which to choose.The AD9512 is ideally suited for data converter clocking applications where maximum converter performance is achieved with sub-picosecond jitter encode signals.The AD9512 is available in a 48-lead LFCSP and is specified from -40?C to +85?C. The part may be run from a single 3.3 V supply. ApplicationsLow jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDS, DDC, DUC, MxFE? ConvertersWireless infrastructure transceiversHigh performance instrumentationBroadband infrastructure

The AD9516-2?provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 2.05 GHz to 2.33 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz can be used.The AD9516-2 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements. The AD9516-2 features six LVPECL outputs (in three pairs) and four LVDS outputs (in two pairs). Each LVDS output can be reconfigured as two CMOS outputs. The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz.Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow a range of divisions up to a maximum of 1024.The AD9516-0 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5 V. A separate LVPECL power supply can be from 2.5 V to 3.3 V (nominal).The AD9516-2 is specified for operation over the standard industrial range of ?40?C to +85?C.APPLICATIONS Low jitter, low phase noise clock distribution 10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4 Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation

The AD9516-4?provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 1.45 GHz to 1.80 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz can be used.The AD9516-4 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements.The AD9516-4 features six LVPECL outputs (in three pairs) and four LVDS outputs (in two pairs). Each LVDS output can be reconfigured as two CMOS outputs. The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz.Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow a range of divisions, up to a maximum of 1024.The AD9516-4 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP to 5 V. A separate LVPECL power supply can be from 2.5 V to 3.3 V (nominal).The AD9516-4 is specified for operation over the industrial range of ?40?C to +85?C.APPLICATIONS Low jitter, low phase noise clock distribution 10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4 Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation?

The AD9516-5?provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL that can be used with an external VCO/VCXO of up to 2.4 GHz.The AD9516-5 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit otherapplications with demanding phase noise and jitter requirements.The AD9516-5 features six LVPECL outputs (in three pairs)and four LVDS outputs (in two pairs). Each LVDS output canbe reconfigured as two CMOS outputs. The LVPECL outputsoperate to 1.6 GHz, the LVDS outputs operate to 800 MHz, andthe CMOS outputs operate to 250 MHz.Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division forthe LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allowa range of divisions up to a maximum of 1024.The AD9516-5 is available in a 64-lead LFCSP and can beoperated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5.5 V. A separate LVPECL power supply can be from 2.375 V to 3.6 V (nominal).The AD9516-5 is specified for operation over the industrial range of ?40?C to +85?C.For applications requiring an integrated EEPROM, or needing additional outputs, the AD9520-5?and AD9522-5?are available.APPLICATIONS Low jitter, low phase noise clock distribution 10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4 Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation