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AD9125-M5372-EBZ

Analog Devices Inc.
The AD9125 is a dual, 16-bit, high dynamic range TxDAC+? digital-to-analog converter (DAC) that provides a sample rate of 1000 MSPS, permitting a multicarrier generation up to the Nyquist frequency. It includes features optimized for direct conversion transmit applications, including complex digital modulation, and gain and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators, such as the ADL537x F-MOD series from Analog Devices, Inc. A 4-wire serial port interface allows programming/readback of many internal parameters. Full-scale output current can be programmed over a range of 8.7 mA to 31.7 mA. The AD9125 comes in a 72-lead LFCSP.PRODUCT HIGHLIGHTS Ultralow noise and intermodulation distortion (IMD) enable high quality synthesis of wideband signals from baseband to high intermediate frequencies. A proprietary DAC output switching technique enhances dynamic performance. The current outputs are easily configured for various single-ended or differential circuit topologies. Flexible CMOS digital interface allows the standard 32-wire bus to be reduced to a 16-wire bus.APPLICATIONS Wireless infrastructure W-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM, LTE Digital high or low IF synthesis Transmit diversity Wideband communications: LMDS/MMDS, point-to-point Cable modem termination systems

AD9142A-M5372-EBZ

Analog Devices Inc.
The AD9142A is a dual, 16-bit, high dynamic range digital-to-analog converter (DAC) that provides a sample rate of 1600 MSPS, permitting a multicarrier generation up to the Nyquist frequency. The AD9142A TxDAC+? includes features optimized for direct conversion transmit applications, including complex digital modulation, input signal power detection, and gain, phase, and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators, such as the ADL537x F-MOD series and the ADRF670x series from Analog Devices, Inc. A 3-wire serial port interface provides for the programming/readback of many internal parameters. Full-scale output current can be programmed over a range of 9 mA to 33 mA. The AD9142A is available in a 72-lead LFCSP.PRODUCT HIGHLIGHTS Wide signal bandwidth (BW) enables emerging wideband and multiband wireless applications. Advanced low spurious and distortion design techniques provide high quality synthesis of wideband signals from baseband to high intermediate frequencies. Very small inherent latency variation simplifies both software and hardware design in the system. It allows easy multichip synchronization for most applications. New low power architecture improves power efficiency (mW/MHz/channel) by 30%. Input signal power and FIFO error detection simplify designs for downstream analog circuitry protection. Programmable transmit enable function allows easy design balance between power consumption and wakeup time.APPLICATIONS Wireless communications: 3G/4G and MC-GSM base stations, wideband repeaters, software defined radios Wideband communications: point-to-point, LMDS/MMDS Transmit diversity/MIMO Instrumentation Automated test equipment

AD9142A-M5375-EBZ

Analog Devices Inc.
The AD9142A is a dual, 16-bit, high dynamic range digital-to-analog converter (DAC) that provides a sample rate of 1600 MSPS, permitting a multicarrier generation up to the Nyquist frequency. The AD9142A TxDAC+? includes features optimized for direct conversion transmit applications, including complex digital modulation, input signal power detection, and gain, phase, and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators, such as the ADL537x F-MOD series and the ADRF670x series from Analog Devices, Inc. A 3-wire serial port interface provides for the programming/readback of many internal parameters. Full-scale output current can be programmed over a range of 9 mA to 33 mA. The AD9142A is available in a 72-lead LFCSP.PRODUCT HIGHLIGHTS Wide signal bandwidth (BW) enables emerging wideband and multiband wireless applications. Advanced low spurious and distortion design techniques provide high quality synthesis of wideband signals from baseband to high intermediate frequencies. Very small inherent latency variation simplifies both software and hardware design in the system. It allows easy multichip synchronization for most applications. New low power architecture improves power efficiency (mW/MHz/channel) by 30%. Input signal power and FIFO error detection simplify designs for downstream analog circuitry protection. Programmable transmit enable function allows easy design balance between power consumption and wakeup time.APPLICATIONS Wireless communications: 3G/4G and MC-GSM base stations, wideband repeaters, software defined radios Wideband communications: point-to-point, LMDS/MMDS Transmit diversity/MIMO Instrumentation Automated test equipment

AD9144-FMC-EBZ

Analog Devices Inc.
The AD9144 is a quad, 16-bit, high dynamic range digital-to-analog converter (DAC) that provides a maximum sample rate of 2.8 GSPS, permitting a multicarrier generation up to the Nyquist frequency. The DAC outputs are optimized to interface seamlessly with the ADRF6720 analog quadrature modulator (AQM) from Analog Devices, Inc. An optional 3-wire or 4-wire serial port interface (SPI) provides for programming/readback of many internal parameters. Full-scale output current can be programmed over a typical range of 13.9 mA to 27.0 mA. The AD9144 is available in an 88-lead LFCSP.Product Highlights Greater than 1 GHz, ultrawide complex signal bandwidth enables emerging wideband and multiband wireless applications. Advanced low spurious and distortion design techniques provide high quality synthesis of wideband signals from baseband to high intermediate frequencies. JESD204B Subclass 1 support simplifies multichip synchronization in software and hardware design. Fewer pins for data interface width with a serializer/deserializer (SERDES) JESD204B eight-lane interface. Programmable transmit enable function allows easy design balance between power consumption and wake-up time. Small package size with 12 mm ? 12 mm footprint.Applications Wireless communications 3G/4G W-CDMA base stations Wideband repeaters Software defined radios Wideband communications Point-to-point Local multipoint distribution service (LMDS) and multichannel multipoint distribution service (MMDS) Transmit diversity, multiple input/multiple output (MIMO) Instrumentation Automated test equipment

AD9152-FMC-EBZ

Analog Devices Inc.
The AD9152 is a dual, 16-bit, high dynamic range digital-to-analog converter (DAC) that provides a maximum sample rate of 2.25 GSPS, permitting a multicarrier generation up to the Nyquist frequency. The DAC outputs are optimized to interface seamlessly with the ADRF6720 analog quadrature modulator (AQM)from Analog Devices, Inc. An optional 3-wire or 4-wire serial port interface (SPI) provides for programming/readback of many internal parameters. The full-scale output current can be programmed over a range of 4 mA to 20 mA. The AD9152 isavailable in a 56-lead LFCSP. The AD9152 is a member of theTxDAC+? family.Product Highlights Ultrawide signal bandwidth enables emerging wideband and multiband wireless applications. Advanced low spurious and distortion design techniques provide high quality synthesis of wideband signals from baseband to high intermediate frequencies. JESD204B Subclass 1 support simplifies multichip synchronization in software and hardware design. Fewer pins for data interface width with the serializer/deserializer (SERDES) JESD204B four-lane interface. Programmable transmit enable function allows easy design balance between power consumption and wake-up time. Small package size with an 8 mm ? 8 mm footprint. ?Applications Wireless communications Multicarrier LTE and GSM base stations Wideband repeaters Software defined radios Wideband communications Point to point microwave radios LMDS/MMDS Transmit diversity, multiple input/multiple output (MIMO) Instrumentation Automated test equipment

AD9154-FMC-EBZ

Analog Devices Inc.
The AD9154 is a quad, 16-bit, high dynamic range digital-to-analog converter (DAC) that provides a maximum sample rate of 2.4 GSPS, permitting multicarrier generation up to the Nyquist frequency in baseband mode. The AD9154 includes features optimized for direct conversion transmit applications including complex digital modulation, input signal power detection, and gain, phase, and offset compensation. The DAC outputs are?optimized to interface seamlessly with the ADRF6720-27 radio?frequency quadrature modulator (AQM) from Analog Devices,?Inc. In mix mode, the AD9154 DAC can reconstruct carriers in the second and third Nyquist Zones. A serial port interface (SPI)?provides the programming/readback of internal parameters. The full-scale output current can be programmed over a range of 4 mA to 20 mA. The AD9154 is available in two different?88-lead LFCSP packages.PRODUCT HIGHLIGHTS? Ultrawide signal bandwidth enables emerging wideband and multiband wireless applications. Advanced low spurious and distortion design techniques provide high quality synthesis of wideband signals from baseband to high intermediate frequencies. JESD204B Subclass 1 support simplifies multichip synchronization. Small package size with a 12 mm ? 12 mm footprint.APPLICATIONS Wireless communications Multicarrier LTE and GSM base stations Wideband repeaters Software defined radios Wideband communications Point to point microwave radio Transmit diversity, multiple input/multiple output (MIMO) Instrumentation Automated test equipment

AD9166-FMC-EBZ

Analog Devices Inc.
The AD91661 is a high performance, wideband, on-chip vector signal generator composed of a high speed JESD204B serializer/deserializer (SERDES) interface, a flexible 16-bit digital datapath, a inphase/quadrature (I/Q) digital-to-analog converter (DAC) core, and an integrated differential to single-ended outputbuffer amplifier, matched to a 50 ? load up to 10 GHz.The DAC core is based on a quad-switch architecture, which is configurable to increase the effective DAC core update rate of up to 12.8 GSPS from a 6.4 GHz DAC sampling clock, with an analog output bandwidth of true dc to 9.0 GHz, typically. The digital datapath includes multiple interpolation filter stages, a direct digital synthesizer (DDS) block with multiple numerically controlled oscillators (NCOs) supporting fast frequency hopping (FFH), and additional FIR85 and inverse sinc filter stages to allow flexible spectrum planning.The differential to single-ended buffer eliminates the need for a wideband balun, and supports the full analog output bandwidth of the DAC core. DC coupling the output allows baseband waveform generation without the need for external bias tees or similar circuitry, which makes the AD9166 uniquely suited for the mostdemanding high speed ultrawideband RF transmit applications. The various filter stages enable the AD9166 to be configured for lower data rates, while maintaining higher DAC clock rates to ease the filtering requirements and reduce the overall system size, weight, and power.The data interface receiver consists of up to eight JESD204B SERDES lanes, each capable of carrying up to 12.5 Gbps. To enable maximum flexibility, the receiver is fully configurable according to the data rate, number of SERDES lanes, and lane mapping required by the JESD204B transmitter.In 2? nonreturn-to-zero (NRZ) mode of operation (with FIR85 enabled), the AD9166 can reconstruct RF carriers from true dc to the edge of the third Nyquist zone, or an analog bandwidth of true dc up to 9 GHz.In mix mode, the AD9166 can reconstruct RF carriers in the second and third Nyquist zones while consuming lower power and maintaining a performance comparable to 2? NRZ mode.In baseband modes, such as return-to-zero (RZ) and 1? NRZ, the AD9166 is ideal to reconstruct RF carriers from true dc to the edge of the first Nyquist zone while consuming lower power compared to 2? NRZ mode.The quadrature DDS block can be configured as a digital upconverter to upconvert I/Q data samples to the desired location across the spectrum, in all three Nyquist zones.The DDS also consists of a bank of 32 numerically controlled oscillators (NCOs), each with its own 32-bit phase accumulator. When combined with a 100 MHz serial peripheral interface (SPI), the DDS allows a phase coherent FFH, with a phase settling time as low as 300 ns.The AD9166 is configured using a common SPI interface that monitors the status of all registers. The AD9166 is offered in a 324-ball, 15 mm ? 15 mm, 0.8 mm pitch BGA_ED package.Product Highlights High dynamic range and signal reconstruction bandwidth supports RF signal synthesis of up to 9 GHz. Fully supports zero IF and other dc-coupled applications. Up to an eight-lane JESD204B SERDES interface, with various features to allow flexibility when interfacing to a JESD204B transmitter.Applications Instrumentation: automated test equipment, electronic test and measurement, arbitrary waveform generators Electronic warfare: radars, jammers Broadband communications systems Local oscillator drivers1 Protected by U.S. Patents 6,842,132 and 7,796,971.

AD9211-300EBZ

Analog Devices Inc.
The AD9211 is a 10-bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. The product operates at up to a 300 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a track-and-hold (T/H) and voltage reference, are included on the chip to provide a complete signal conversion solution.The ADC requires a 1.8 V analog voltage supply and a differential clock for full performance operation. The digital outputs are LVDS (ANSI-644) compatible and support either twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing.Fabricated on an advanced CMOS process, the AD9211 is available in a 56-lead LFCSP, specified over the industrial temperature range (?40?C to +85?C).PRODUCT HIGHLIGHTS High Performance?Maintains 60.1 dBFS SNR @ 300 MSPS with a 70 MHz input. Low Power?Consumes only 410 mW @ 300 MSPS. Ease of Use?LVDS output data and output clock signal allow interface to current FPGA technology. The on-chip reference and sample-and-hold provide flexibility in system design. Use of a single 1.8 V supply simplifies system power supply design. Serial Port Control?Standard serial port interface supports various product functions, such as data formatting, disabling the clock duty cycle stabilizer, power-down, gain adjust, and output test pattern generation. Pin-Compatible Family?12-bit pin-compatible family offered as AD9230.APPLICATIONS Wireless and wired broadband communications Cable reverse path Communications test equipment Radar and satellite subsystems Power amplifier linearization

AD9255-80EBZ

Analog Devices Inc.
The AD9255 is a 14-bit, 125 MSPS analog-to-digital converter (ADC). The AD9255 is designed to support communications applications where high performance combined with low cost, small size, and versatility is desired.The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic to provide 14-bit accuracy at 125 MSPS data rates and guarantees no missing codes over the full operating temperature range.The ADC features a wide bandwidth differential sample-and-hold analog input amplifier supporting a variety of user-selectable input ranges. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling single-channel inputs at frequencies well beyond the Nyquist rate. Combined with power and cost savings over previously available ADCs, the AD9255 is suitable for applications in communications, instrumentation, and medical imaging.A differential clock input controls all internal conversion cycles. A duty cycle stabilizer provides the means to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance over a wide range of input clock duty cycles. An integrated voltage reference eases design considerations.The ADC output data format is either parallel 1.8 V CMOS or LVDS (DDR). A data output clock is provided to ensure proper latch timing with receiving logic.Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface. Flexible power-down options allow significant power savings, when desired. An optional on-chip dither function is available to improve SFDR performance with low power analog input signals.The AD9255 is available in a Pb-free, 48-lead LFCSP and is specified over the industrial temperature range of ?40?C to +85?C.PRODUCT HIGHLIGHTS On-chip dither option for improved SFDR performance with low power analog input. Proprietary differential input that maintains excellent SNR performance for input frequencies up to 300 MHz. Operation from a single 1.8 V supply and a separate digital output driver supply accommodating 1.8 V CMOS or LVDS outputs. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, test modes, and voltage reference mode. ?Pin compatibility with the AD9265, allowing a simple migration up to 16 bits.Applications Communications Multimode digital receivers (3G) GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, and TD-SCDMA Smart antenna systems General-purpose software radios Broadband data applications Ultrasound equipment

AD9286-500EBZ

Analog Devices Inc.
The AD9286 is an 8-bit, monolithic sampling, analog-to-digital converter (ADC) that supports interleaved operation and is optimized for low cost, low power, and ease of use. Each ADC operates at up to a 250 MSPS conversion rate with outstanding dynamic performance.The AD9286 takes a single sample clock and, with an on-chip clock divider, time interleaves the two ADC cores (each running at one-half the clock frequency) to achieve the rated 500 MSPS. By using the SPI, the user can accurately adjust the timing of the sampling edge per ADC to minimize the image spur energy.The ADC requires a single 1.8 V supply and an encode clock for full performance operation. No external reference components are required for many applications. The digital outputs are LVDS compatible.The AD9286 is available in a Pb-free, 48-lead LFCSP that is specified over the industrial temperature range of ?40?C to +85?C. PRODUCT HIGHLIGHTS Integrated 8-bit, 500 MSPS ADC. Single 1.8 V supply operation with LVDS outputs. Power-down option controlled via a pin-programmable setting.?APPLICATIONS Battery-powered instruments Handheld scope meters Low cost digital oscilloscopes OTS: video over fiber

AD9512/PCBZ

Analog Devices Inc.
The AD9512 provides a multi-output clock distribution function for input signals up to 1.6 GHz. The design emphasizes low jitter and low phase noise in order to maximize data converter clocking performance. Three independent LVPECL and two LVDS clock outputs operate to 1.2 GHz and 800 MHz respectively. Optional CMOS clock outputs available to 250 MHz. Each output has a programmable divider, which may be bypassed or set to divide by any integer up to 32.Each divider allows the user to change the phase of one clock output relative to another clock output. This phase select functions as a coarse timing adjustment. One output also features a programmable delay element with a user-selected, fullscale range to 10 ns. This fine tuning delay block is programmed with a 5-bit word, which gives the user 32 possible delays from which to choose.The AD9512 is ideally suited for data converter clocking applications where maximum converter performance is achieved with sub-picosecond jitter encode signals.The AD9512 is available in a 48-lead LFCSP and is specified from -40?C to +85?C. The part may be run from a single 3.3 V supply. ApplicationsLow jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDS, DDC, DUC, MxFE? ConvertersWireless infrastructure transceiversHigh performance instrumentationBroadband infrastructure

AD9516-2/PCBZ

Analog Devices Inc.
The AD9516-2?provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 2.05 GHz to 2.33 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz can be used.The AD9516-2 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements. The AD9516-2 features six LVPECL outputs (in three pairs) and four LVDS outputs (in two pairs). Each LVDS output can be reconfigured as two CMOS outputs. The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz.Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow a range of divisions up to a maximum of 1024.The AD9516-0 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5 V. A separate LVPECL power supply can be from 2.5 V to 3.3 V (nominal).The AD9516-2 is specified for operation over the standard industrial range of ?40?C to +85?C.APPLICATIONS Low jitter, low phase noise clock distribution 10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4 Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation

AD9516-4/PCBZ

Analog Devices Inc.
The AD9516-4?provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 1.45 GHz to 1.80 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz can be used.The AD9516-4 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements.The AD9516-4 features six LVPECL outputs (in three pairs) and four LVDS outputs (in two pairs). Each LVDS output can be reconfigured as two CMOS outputs. The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz.Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow a range of divisions, up to a maximum of 1024.The AD9516-4 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP to 5 V. A separate LVPECL power supply can be from 2.5 V to 3.3 V (nominal).The AD9516-4 is specified for operation over the industrial range of ?40?C to +85?C.APPLICATIONS Low jitter, low phase noise clock distribution 10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4 Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation?

AD9516-5/PCBZ

Analog Devices Inc.
The AD9516-5?provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL that can be used with an external VCO/VCXO of up to 2.4 GHz.The AD9516-5 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit otherapplications with demanding phase noise and jitter requirements.The AD9516-5 features six LVPECL outputs (in three pairs)and four LVDS outputs (in two pairs). Each LVDS output canbe reconfigured as two CMOS outputs. The LVPECL outputsoperate to 1.6 GHz, the LVDS outputs operate to 800 MHz, andthe CMOS outputs operate to 250 MHz.Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division forthe LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allowa range of divisions up to a maximum of 1024.The AD9516-5 is available in a 64-lead LFCSP and can beoperated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5.5 V. A separate LVPECL power supply can be from 2.375 V to 3.6 V (nominal).The AD9516-5 is specified for operation over the industrial range of ?40?C to +85?C.For applications requiring an integrated EEPROM, or needing additional outputs, the AD9520-5?and AD9522-5?are available.APPLICATIONS Low jitter, low phase noise clock distribution 10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4 Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation

AD9517-4A/PCBZ

Analog Devices Inc.
The AD9517-4?provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 1.45 GHz to 1.80 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz can be used.The AD9517-4 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements.The AD9517-4 features four LVPECL outputs (in two pairs) and four LVDS outputs (in two pairs). Each LVDS output can be reconfigured as two CMOS outputs. The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz.For applications that require additional outputs, a crystal reference input, zero-delay, or EEPROM for automatic configuration at startup, the AD9520 and AD9522 are available. In addition, the AD9516 and AD9518 are similar to the AD9517 but have a different combination of outputs.Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow a range of divisions up to a maximum of 1024.The AD9517-4 is available in a 48-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5 V. A separate LVPECL power supply can be from 2.5 V to 3.3 V (nominal).The AD9517-4 is specified for operation over the industrial range of ?40?C to +85?C.APPLICATIONS Low jitter, low phase noise clock distribution 10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4 Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation

AD9520-1/PCBZ

Analog Devices Inc.
The AD9520-11 provides a multioutput clock distributionfunction with subpicosecond jitter performance, along with anon-chip PLL and VCO. The on-chip VCO tunes from 2.27 GHzto 2.65 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHzcan also be used.The AD9520 serial interface supports both SPI and I2C? ports. An in-package EEPROM can be programmed through the serial interface and store user-defined register settings for power-up and chip reset.The AD9520 features 12 LVPECL outputs in four groups. Anyof the 1.6 GHz LVPECL outputs can be reconfigured as two250 MHz CMOS outputsEach group of outputs has a divider that allows both the divideratio (from 1 to 32) and the phase (coarse delay) to be set.The AD9520 is available in a 64-lead LFCSP and can be operatedfrom a single 3.3 V supply. The external VCO can have anoperating voltage up to 5.5 V. A separate output driver powersupply can be from 2.375 V to 3.465 VThe AD9520 is specified for operation over the standard industrialrange of ?40?C to +85?C.1The AD9520 is used throughout this data sheet to refer to all the members of the AD9520 family. However, when AD9520-1 is used, it is referring to that specificmember of the AD9520 family.ApplicationsLow jitter, low phase noise clock distributionClock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocolsForward error correction (G.710)Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEsHigh performance wireless transceiversATE and high performance instrumentationBroadband infrastructures

AD9520-2/PCBZ

Analog Devices Inc.
The AD9520-2 provides a multioutput clock distributionfunction with subpicosecond jitter performance, along with anon-chip PLL and VCO. The on-chip VCO tunes from 2.02 GHzto 2.335 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHzcan also be used.The AD9520-2 serial interface supports both SPI and I2C?ports.An in-package EEPROM, which can be programmed through theserial interface, can store user-defined register settings forpower-up and chip reset.The AD9520-2 features 12 LVPECL outputs in four groups. Anyof the 1.6 GHz LVPECL outputs can be reconfigured as two250 MHz CMOS outputs. If an application requires LVDSdrivers instead of LVPECL drivers, refer to the AD9522-2.Each group of three outputs has a divider that allows both thedivide ratio (from 1 to 32) and the phase offset or coarse timedelay to be set.The AD9520-2 is available in a 64-lead LFCSP and can be operatedfrom a single 3.3 V supply. The external VCO can have anoperating voltage of up to 5.5 V. A separate output driver powersupply can be from 2.375 V to 3.465 V.The AD9520-2 is specified for operation over the standardindustrial range of ?40?C to +85?C.Applications Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10GFC, Synchronous Ethernet, OTU2/3/4 Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation Broadband infrastructures

AD9520-3/PCBZ

Analog Devices Inc.
The AD9520-31 provides a multioutput clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 1.72 GHz to 2.25 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHz can also be used.The AD9520 serial interface supports both SPI and I2C? ports. An in-package EEPROM can be programmed through the serial interface and store user-defined register settings for power-up and chip reset.The AD9520 features 12 LVPECL outputs in four groups. Any of the 1.6 GHz LVPECL outputs can be reconfigured as two 250 MHz CMOS outputs.Each group of outputs has a divider that allows both the divide ratio (from 1 to 32) and the phase (coarse delay) to be set.The AD9520 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. The external VCO can have an operating voltage up to 5.5 V. A separate output driver power supply can be from 2.375 V to 3.465 V.The AD9520 is specified for operation over the standard industrial range of ?40?C to +85?C.1The AD9520 is used throughout this data sheet to refer to all the members of the AD9520 family. However, when AD9520-3 is used, it is referring to that specific member of the AD9520 family.Applications Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation Broadband infrastructures

AD9522-1/PCBZ

Analog Devices Inc.
The AD9522-11 provides a multioutput clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 2.27 GHz to 2.65 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHz can also be used.The AD9522 serial interface supports both SPI and I2C? ports. An in-package EEPROM can be programmed through the serial interface and store user-defined register settings for power-up and chip reset.The AD9522 features 12 LVDS outputs in four groups. Any of the 800 MHz LVDS outputs can be reconfigured as two 250 MHz CMOS outputs.Each group of outputs has a divider that allows both the divide ratio (from 1 to 32) and the phase (coarse delay) to be set.The AD9522 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. The external VCO can have an operating voltage up to 5.5 V.The AD9522 is specified for operation over the standard industrial range of ?40?C to +85?C.The AD9520-1 is an equivalent part to the AD9522-1 featuring LVPECL/CMOS drivers instead of LVDS/CMOS drivers.1The AD9522 is used throughout this data sheet to refer to all the members of the AD9522 family. However, when AD9522-1 is used, it is referring to that specific member of the AD9522 family.ApplicationsLow jitter, low phase noise clock distributionClock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocolsForward error correction (G.710)Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEsHigh performance wireless transceiversATE and high performance instrumentationBroadband infrastructures

AD9523-1/PCBZ

Analog Devices Inc.
The AD9523-1 provides a low power, multi-output, clock distribution function with low jitter performance, along with an on-chip PLL and VCO with two VCO dividers. The on-chip VCO tunes from 2.94 GHz to 3.1 GHz.The AD9523-1 is designed to support the clock requirements for long term evolution (LTE) and multicarrier GSM base station designs. It relies on an external VCXO to provide the reference jitter cleanup to achieve the restrictive low phase noise requirements necessary for acceptable data converter SNR performance.The input receivers, oscillator, and zero delay receiver provide both single-ended and differential operation. When connected to a recovered system reference clock and a VCXO, the device generates 14 low noise outputs with a range of 1 MHz to 1 GHz, and one dedicated buffered output from the input PLL (PLL1). The frequency and phase of one clock output relative to another clock output can be varied by means of a divider phase select function that serves as a jitter-free, coarse timing adjustment in increments that are equal to half the period of the signal coming out of the VCO.An in-package EEPROM can be programmed through the serial interface to store user-defined register settings for power-up and chip reset.APPLICATIONS LTE and multicarrier GSM base stations Wireless and broadband infrastructure Medical instrumentation Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction (G.710) High performance wireless transceivers ATE and high performance instrumentation

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