The ADP5054 combines four high performance buck regulators in a 48-lead LFCSP package that meets demanding performance and board space requirements. The device enables direct connection to high input voltages of up to 15.5 V with no preregulators.Channel 1 and Channel 2 integrate high-side power metal-oxide semiconductor field effect transistors (MOSFETs) and low-side MOSFET drivers. External NFETs can be used in low-side power devices to achieve an efficiency optimized solution and to deliver a programmable output current of 2 A, 4 A, or 6 A. Combining Channel 1 and Channel 2 in a parallel configuration provides a single output with up to 12 A of current.Channel 3 and Channel 4 integrate both high-side and low-side MOSFETs to deliver an output current of 2.5 A. Combining Channel 3 and Channel 4 in a parallel configuration can provide a single output with up to 5 A of current.The switching frequency of the ADP5054 can be programmed or synchronized to an external clock from 250 kHz to 2 MHz, and an individual ?? frequency configuration is available for each channel.The ADP5054 contains an individual precision enable pin on each channel for easy power-up sequencing. The internal low 1/f noise reference is implemented in the ADP5054 for noise sensitive applications.Applications FPGA and processor applications Small cell base stations Security and surveillance Medical applications

The ADP5070 is a dual high performance dc-to-dc regulator that generates independently regulated positive and negative rails.The input voltage range of 2.85 V to 15 V supports a wide variety of applications. The integrated main switch in both regulators enables generation of an adjustable positive output voltage up to +39 V and a negative output voltage down to ?39 V below input voltage.The ADP5070 operates at a pin selected 1.2 MHz/2.4 MHz switching frequency. The ADP5070 can synchronize with an external oscillator from 1.0 MHz to 2.6 MHz to ease noise filtering in sensitive applications. Both regulators implement programmable slew rate control circuitry for the MOSFET driver stage to reduce electromagnetic interference (EMI).Flexible start-up sequencing is provided with the options of manual enable, simultaneous mode, positive supply first, and negative supply first.The ADP5070 includes a fixed internal or resistor programmable soft start timer to prevent inrush current at power-up. During shutdown, both regulators completely disconnect the loads from the input supply to provide a true shutdown.Other key safety features in the ADP5070 include overcurrent protection (OCP), overvoltage protection (OVP), thermal shutdown (TSD), and input undervoltage lockout (UVLO).The ADP5070 is available in a 20-lead LFCSP or in a 20-lead TSSOP and is rated for a ?40?C to +125?C junction temperature range.Applications Bipolar amplifiers, ADCs, DACs and multiplexers Charge-coupled device (CCD) bias supply Optical module supply RF power amplifier (PA) bias

The ADP5071 is a dual high performance dc-to-dc regulator that generates independently regulated positive and negative rails.The input voltage range of 2.85 V to 15 V supports a wide variety of applications. The integrated main switch in both regulators enables generation of an adjustable positive output voltage up to +39 V and a negative output voltage down to ?39 V below input voltage.The ADP5071 operates at a pin selected 1.2 MHz/2.4 MHz switching frequency. The ADP5071 can synchronize with an external oscillator from 1.0 MHz to 2.6 MHz to ease noise filtering in sensitive applications. Both regulators implement programmable slew rate control circuitry for the MOSFET driver stage to reduce electromagnetic interference (EMI).Flexible start-up sequencing is provided with the options of manual enable, simultaneous mode, positive supply first, and negative supply first.The ADP5071 includes a fixed internal or resistor programmable soft start timer to prevent inrush current at power-up. During shutdown, both regulators completely disconnect the loads from the input supply to provide a true shutdown.Other key safety features in the ADP5071 include overcurrent protection (OCP), overvoltage protection (OVP), thermal shutdown (TSD), and input undervoltage lockout (UVLO).The ADP5071 is available in a 20-lead LFCSP or in a 20-lead TSSOP and is rated for a ?40?C to +125?C junction temperature range.Applications Bipolar amplifiers, ADCs, DACs, and multiplexers Charge-coupled device (CCD) bias supply Optical module supply RF power amplifier (PA) bias

The ADP5091/ADP5092 are intelligent, integrated energy harvesting, ultralow power management unit (PMU) solutions that convert dc power from PV cells or TEGs. These devices charge storage elements such as rechargeable Li-Ion batteries, thin film batteries, super capacitors, or conventional capacitors, and power up small electronic devices and battery free systems.The ADP5091/ADP5092 provide efficient conversion of the harvested limited power from a 6 ?W to 600 mW range with submicrowatt operation losses. With the internal cold start circuit, the regulator can start operating at an input voltage as low as 380 mV. After cold startup, the regulator is functional at an input voltage range of 0.08 V to 3.3 V. An additional 150 mA regulated output can be programmed by an external resistor divider or the VID pin.The MPPT control keeps the input voltage ripple in a fixed range to maintain stable dc-to-dc boost conversion. The dynamic sensing mode and no sensing mode, both programming regulation points of the input voltage, allow extraction of the highest possible energy from the harvester. A programmable minimum operation threshold enables boost shutdown during a low input condition.As a low light indicator for a microprocessor, the LLD pin of the ADP5091 is the MINOP comparator output. However, the REG_GOOD flag of the ADP5092 monitors the REG_OUT voltage. In addition, the DIS_SW pin can temporarily shut down the boost regulator and is RF transmission friendly.The charging control function of the ADP5091/ADP5092 protects the rechargeable energy storage, which is achieved by monitoring the battery voltage with the programmable charging termination voltage and the shutdown discharging voltage. In addition, a programmable PGOOD flag monitors the SYS voltage.An optional primary cell battery can be connected and managed by an integrated power path management control block that is programmable to switch the power source from the energy harvester, rechargeable battery, and primary cell battery.The ADP5091/ADP5092 are available in a 24-lead LFCSP and are rated for a ?40?C to +125?C temperature range.Applications Photovoltaic (PV) cell energy harvesting Thermoelectric generators (TEGs) energy harvesting Industrial monitoring Self powered wireless sensor devices Portable and wearable devices with energy harvesting

The AD9371 is a highly integrated, wideband RF transceiveroffering dual channel transmitters and receivers, integrated synthesizers, and digital signal processing functions. The ICdelivers a versatile combination of high performance and low power consumption required by 3G/4G micro and macro BTSequipment in both FDD and TDD applications. The AD9371operates from 300 MHz to 6000 MHz, covering most of the licensed and unlicensed cellular bands. The IC supports receiver bandwidths up to 100 MHz. It also supports observation receiver and transmit synthesis bandwidths up to 250 MHz to accommodate digital correction algorithms.The transceiver consists of wideband direct conversion signalpaths with state-of-the-art noise figure and linearity. Each complete receiver and transmitter subsystem includes dc offset correction, quadrature error correction (QEC), and programmable digitalfilters, eliminating the need for these functions in the digitalbaseband. Several auxiliary functions such as an auxiliary analog-to-digital converter (ADC), auxiliary digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) are integratedto provide additional monitoring and control capability.An observation receiver channel with two inputs is included to monitor each transmitter output and implement interference mitigation and calibration applications. This channel also connects to three sniffer receiver inputs that can monitor radio activity in different bands.The high speed JESD204B interface supports lane rates up to 6144 Mbps. Four lanes are dedicated to the transmitters and four lanes are dedicated to the receiver and observation receiver channels.The fully integrated phase-locked loops (PLLs) provide high performance, low power fractional-N frequency synthesis forthe transmitter, the receiver, the observation receiver, and theclock sections. Careful design and layout techniques provide theisolation demanded in high performance base station applications.All voltage controlled oscillator (VCO) and loop filter components are integrated to minimize the external component count. A 1.3 V supply is required to power the core of the AD9371, anda standard 4-wire serial port controls it. Other voltage supplies provide proper digital interface levels and optimize transmitterand auxiliary converter performance. The AD9371 is packaged in a12 mm ? 12 mm, 196-ball chip scale ball grid array (CSP_BGA).Applications 3G/4G micro and macro base stations (BTS) 3G/4G multicarrier picocells? FDD and TDD active antenna systems? Microwave, nonline of sight (NLOS) backhaul systems

The ADXL213 is a low cost, low power, complete dual axis accelerometer with signal conditioned, duty cycle modulated outputs, all on a single monolithic IC. The ADXL213 measures acceleration with a full-scale range of ?1.2 g (typical). The ADXL213 can measure both dynamic acceleration (e.g., vibration) and static acceleration (e.g., gravity).The outputs are digital signals whose duty cycles (ratio of pulse width to period) are proportional to acceleration (30%/g). The duty cycle outputs can be directly measured by a microcontroller without an A/D converter or glue logic.Innovative design techniques are used to ensure high zero g bias stability (typically better than 0.25 mg/?C), as well as tight sensitivity stability (typically better than 50 ppm/?C).The typical noise floor is 160 ?g/?, allowing signals below 1 mg (0.06? of inclination) to be resolved in tilt sensing applications using narrow bandwidths (The user selects the bandwidth of the accelerometer usingcapacitors CX and CYM at the XFILT and YFILT pins. Bandwidths of0.5 Hz to 250 Hz may be selected to suit the application.The ADXL213 is available in a 5mm x 5mm x 2mm, 8-pad hermetic LCC package.ApplicationsAutomotive tilt alarmData projectorsNavigationPlatform stabilization/levelingAlarms and motion detectorsHigh accuracy, 2-axis tilt sensing

DC1010A-C: Demo Board for the LTC2487 16-Bit 2-/4-Channel ΔΣ ADC with PGA, Easy Drive and I2C Interface.

DC1012A-B: Demo Board for the LTC2497 16-Bit 8-/16-Channel ΔΣ ADC with Easy Drive Input Current Cancellation and I2C Interface

The LTC2952 is a power management device that features three main functions: pushbutton on/off control of system power, ideal diode PowerPath? controllers and system monitoring. The LTC2952?s pushbutton input, which provides on/off control of system power, has independently adjustable ON and OFF debounce times. A simple microprocessor interface involving an interrupt signal allows for proper system housekeeping prior to power-down. The ideal diode PowerPath controllers provide automatic low loss switchover between two DC sources by regulating two external P-channel MOSFETs to have a small 20mV forward drop. High reliability systems may utilize the LTC2952?s monitoring features to ensure system integrity. These features include: power-fail, voltage monitoring and ?P watchdog. The LTC2952 operates over a wide operating voltage range to accommodate a large variety of input power supplies. The part?s combination of low 20mV external MOSFET regulation and very low standby current matches battery powered and power conscious application requirements.Applications Desktop and Notebook Computers Portable Instrumentations Cell Phones, PDA and Handheld Computers Servers and Computer Peripherals Battery Backup Systems

The LTC1068 product family consists of four monolithic clock-tunable filter building blocks. Each product contains four matched, low noise, high accuracy 2nd order switched-capacitor filter sections. An external clock tunes the center frequency of each 2nd order filter section. The LTC1068 products differ only in their clock-to-center frequency ratio. The clock-to-center frequency ratio is set to 200:1 (LTC1068-200), 100:1 (LTC1068), 50:1 (LTC1068-50) or 25:1 (LTC1068-25). External resistors can modify the clock-to-center frequency ratio. High performance, quad 2nd order, dual 4th order or 8th order filters can be designed with an LTC1068 family product. Designing filters with an LTC1068 product is fully supported by FilterCAD? filter design software for Windows. The LTC1068 products are available in a 28-pin SSOP surface mount package. A customized version of an LTC1068 family product can be obtained in a 16-lead SO package with internal thin-film resistors. Please contact LTC Marketing for details.Applications Lowpass or Highpass Filters: LTC1068-200, 0.5Hz to 25kHz; LTC1068, 1Hz to 50kHz; LTC1068-50, 2Hz to 50kHz; LTC1068-25, 4Hz to 200kHz Bandpass or Bandreject (Notch) Filters: LTC1068-200, 0.5Hz to 15kHz; LTC1068, 1Hz to 30kHz; LTC1068-50, 2Hz to 30kHz; LTC1068-25, 4Hz to 140kHz

Demonstration circuits 1053A-E through 1053A-H exercise the LTC3526L family of high efficiency synchronous boost converters, and are capable of operating with an input voltage range from 0.8V to 5.5V. The 2 × 2 mm DFN thermally enhanced package, high switching frequency (1MHz or 2MHz) and 550mA internal power switches provide a very tiny solution. The LTC3526L family also features output disconnect, and the input voltage can be greater or less than the output voltage. DC1053A-E features the LTC3526L (Burst mode operation) and the DC1053A-F features the LTC3526LB (Burst mode defeated). Both have a 1MHz switching frequency and use a 4.7µH inductor.

Demonstration circuits 1053A-E through 1053A-H exercise the LTC3526L family of high efficiency synchronous boost converters, and are capable of operating with an input voltage range from 0.8V to 5.5V. The 2 × 2 mm DFN thermally enhanced package, high switching frequency (1MHz or 2MHz) and 550mA internal power switches provide a very tiny solution. The LTC3526L family also features output disconnect, and the input voltage can be greater or less than the output voltage. DC1053A-G features the LTC3526L-2 (Burst mode operation) and the DC1053A-H features the LTC3526LB-2 (Burst mode defeated). Both have a 2MHz switching frequency and use a 2.2µH inductor.

DC1067A-A: Demo Board for the LTC2450 Easy-to-Use, Ultra-Tiny 16-Bit ΔΣ ADC.

The LTC2356-12/LTC2356-14 are 12-bit/14-bit, 3.5Msps serial ADCs with differential inputs. The devices draw only 5.5mA from a single 3.3V supply and come in a tiny 10-lead MSOP package. A Sleep shutdown feature further reduces power consumption to 13?W. The combination of speed, low power and tiny package makes the LTC2356-12/LTC2356-14 suitable for high speed, portable applications.The 80dB common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source.The devices convert ?1.25V to 1.25V bipolar inputs differentially. The absolute voltage swing for AIN+ and AIN? extends from ground to the supply voltage.The serial interface sends out the conversion results during the 16 clock cycles following a CONV rising edge for compatibility with standard serial interfaces. If two additional clock cycles for acquisition time are allowed after the data stream in between conversions, the full sampling rate of 3.5Msps can be achieved with a 63MHz clock. Bits LTC2356-12 12 LTC2356-14 14 Applications Communications Data Acquisition Systems Uninterrupted Power Supplies Multiphase Motor Control Multiplexed Data Acquisition RFID

Demonstration circuit DC1129A is a synchronous step down converter featuring the LTC3610, the high efficiency, high density DC/DC regulator. The input voltage range is from 4.5V to 24V. The output voltage is jumper-selectable and provides 1.2V, 1.5V, 1.8V or 2.5V at 12A load current. The regulator includes the controller and power MOSFETs in the 9mm by 9 mm QFN package.

DC1130A: Demo Board for the LT3477 3A, DC/DC Converter with Dual Rail-to-Rail Current Sense.

DC1140A: Demo Board for LTC3567 High Efficiency USB Power Manager Plus 1A Buck-Boost Converter with I2C Control

The AD9255 is a 14-bit, 125 MSPS analog-to-digital converter (ADC). The AD9255 is designed to support communications applications where high performance combined with low cost, small size, and versatility is desired.The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic to provide 14-bit accuracy at 125 MSPS data rates and guarantees no missing codes over the full operating temperature range.The ADC features a wide bandwidth differential sample-and-hold analog input amplifier supporting a variety of user-selectable input ranges. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling single-channel inputs at frequencies well beyond the Nyquist rate. Combined with power and cost savings over previously available ADCs, the AD9255 is suitable for applications in communications, instrumentation, and medical imaging.A differential clock input controls all internal conversion cycles. A duty cycle stabilizer provides the means to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance over a wide range of input clock duty cycles. An integrated voltage reference eases design considerations.The ADC output data format is either parallel 1.8 V CMOS or LVDS (DDR). A data output clock is provided to ensure proper latch timing with receiving logic.Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface. Flexible power-down options allow significant power savings, when desired. An optional on-chip dither function is available to improve SFDR performance with low power analog input signals.The AD9255 is available in a Pb-free, 48-lead LFCSP and is specified over the industrial temperature range of ?40?C to +85?C.PRODUCT HIGHLIGHTS On-chip dither option for improved SFDR performance with low power analog input. Proprietary differential input that maintains excellent SNR performance for input frequencies up to 300 MHz. Operation from a single 1.8 V supply and a separate digital output driver supply accommodating 1.8 V CMOS or LVDS outputs. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, test modes, and voltage reference mode. ?Pin compatibility with the AD9265, allowing a simple migration up to 16 bits.Applications Communications Multimode digital receivers (3G) GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, and TD-SCDMA Smart antenna systems General-purpose software radios Broadband data applications Ultrasound equipment

The AD9286 is an 8-bit, monolithic sampling, analog-to-digital converter (ADC) that supports interleaved operation and is optimized for low cost, low power, and ease of use. Each ADC operates at up to a 250 MSPS conversion rate with outstanding dynamic performance.The AD9286 takes a single sample clock and, with an on-chip clock divider, time interleaves the two ADC cores (each running at one-half the clock frequency) to achieve the rated 500 MSPS. By using the SPI, the user can accurately adjust the timing of the sampling edge per ADC to minimize the image spur energy.The ADC requires a single 1.8 V supply and an encode clock for full performance operation. No external reference components are required for many applications. The digital outputs are LVDS compatible.The AD9286 is available in a Pb-free, 48-lead LFCSP that is specified over the industrial temperature range of ?40?C to +85?C. PRODUCT HIGHLIGHTS Integrated 8-bit, 500 MSPS ADC. Single 1.8 V supply operation with LVDS outputs. Power-down option controlled via a pin-programmable setting.?APPLICATIONS Battery-powered instruments Handheld scope meters Low cost digital oscilloscopes OTS: video over fiber

The AD9512 provides a multi-output clock distribution function for input signals up to 1.6 GHz. The design emphasizes low jitter and low phase noise in order to maximize data converter clocking performance. Three independent LVPECL and two LVDS clock outputs operate to 1.2 GHz and 800 MHz respectively. Optional CMOS clock outputs available to 250 MHz. Each output has a programmable divider, which may be bypassed or set to divide by any integer up to 32.Each divider allows the user to change the phase of one clock output relative to another clock output. This phase select functions as a coarse timing adjustment. One output also features a programmable delay element with a user-selected, fullscale range to 10 ns. This fine tuning delay block is programmed with a 5-bit word, which gives the user 32 possible delays from which to choose.The AD9512 is ideally suited for data converter clocking applications where maximum converter performance is achieved with sub-picosecond jitter encode signals.The AD9512 is available in a 48-lead LFCSP and is specified from -40?C to +85?C. The part may be run from a single 3.3 V supply. ApplicationsLow jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDS, DDC, DUC, MxFE? ConvertersWireless infrastructure transceiversHigh performance instrumentationBroadband infrastructure