This application report explains how you can configure the SimpleLink™ Bluetooth low energy CC2640 wireless MCU, CC2640R2F wireless MCU and multi-standard CC2650 wireless MCU to run the Bluetooth low energy (BLE) software stack without the need for a 32 kHz crystal.

This application report explains how to configure this mode of operation, what considerations have to be taken to use the internal RC low frequency oscillator (RCOSC_LF) for the Bluetooth low energy peripheral and broadcast (beacon) role devices instead of the 32 kHz crystal, and what impact it has on current consumption. This document assumes the reader is familiar with the concepts described in CC2640 and CC2650 SimpleLink™ Bluetooth® low energy Software Stack Developer's Guide and the CC13xx, CC26xx SimpleLink™ Wireless MCU Technical Reference Manual.

Removing the 32 kHz crystal from a design lowers the bill of material (BOM) cost, reduces the required board space and simplifies procurement.

The XMS432P401R Revision C that is currently sampling is preproduction quality. It has not been released to production, and production quality assurance testing has not been fully completed. These units are intended to be used for early prototyping and evaluation, and they are affected by the advisories in this document. The production units will be marked as MSP432P401x Revision C, and they will not be affected by these advisories.

If you have ever worked with communications, data centers, or enterprise networking equipment—routers, switches, server chassis—you probably have heard the term green-box test. A green-box (GB) test applies to multi-gigabit serial links and is a procedure that seeks to identify the optimum transmitter equalization settings by sweeping these parameters and measuring a corresponding figure of merit (FoM). For systems with hundreds or thousands of high-speed channels, GB testing is often the most reliable way to pinpoint the transmitter settings which enable the system to meet the required bit error rate (BER). This article describes the GB test methodology and its applications.

The Texas Instruments Standard Linear & Logic (SLL) business group uses complex methods to assign device topside marking. These methods ensure that correct component identification is applied at each factory location. End users of the standard components often need to peruse many TI and industry publications to understand the markings. This application report combines topside-marking guidelines and package-outline examples in one document.

This document describes a candidate device, ADC32RFx5, for the next generation (5G) cellular system that shows a total of 800 MHz of Instantaneous Bandwidth (IBW) using Long Term Evolution (LTE) patterns (40 of LTE 20 MHz) processed from Matlab after being captured from TSW14J56 evaluation module out of ADC32RFx5.

There are many of key technologies to help the air interface of 5G deployed in the near future such as enhanced data rate, reduced latency, increased frequency bands with a ultra-wide bandwidth. Massive MIMO (Multi-Input Multi-Output) will give us improved spectral efficiency for multi mobile users within cell, and hybrid beamforming will increase cell coverage for multi users. But, those architectures will increase hardware complexity and power consumption of the system while requiring large number of power-hungry converters. At the same time, massive connectivity for uplink (UL) also should be supported with scalable data rates for 5G system. To show much better spectral efficiency, 800 MHz of IBW is fed into ADC32RFx5 which is a direct RF sampling analog to digital converter (ADC).

Another aspect of 5G is the specification of future waveform which is still under discussion. Orthogonal frequency division multiplexing (OFDM) has been a waveform for 4G system so far but the potential waveform of physical layer for 5G is not defined yet. There are some candidates to be deployed in 5G system in the future, which are filter bank multi carrier (FBMC), universal filtered multi carrier (UFMC), generalized frequency division multiplexing (GFDM) and filtered OFDM (f-OFDM). These kinds of future waveform will handle higher data rate with wider bandwidth than LTE pattern, and also have different filtering and windowing from 4G standards.

The ADC32RFx5 is a family of high performance dual channel 14-bit, 3-Gsps RF ADCs, capable of having input frequencies up to 2.5 GHz and beyond. Designed for high signal-to-noise ratio (SNR), the ADC32RFx5 delivers a noise floor of –155 dBFS/Hz. Together with its exceptional spurious free dynamic range (SFDR) performance, this device can cover even the toughest receiver requirements such as multicarrier GSM and 5G receiver in the future.

This application report describes how to use peripheral boot and Device Firmware Upgrade (DFU) to reduce the time required to load updated binaries to various cores of a Jacinto 6 (DRA7xx) family device.

Reducing power and cost are often two of the most crucial factors when designing a battery-powered system. Reducing power consumption plays an in important role to extend system life by reducing overall system current. Hence, as a result, power reduction paves the way to cut down system cost by reducing the required battery capacity.

This concept readily applies to Internet of Things (IoT) systems and connected products such as wearables, wireless sensors and building automation systems. The life of the growing number of wireless sensor endnodes in the system all are constrained by one thing: power consumption of the end-node. Such sensor end nodes are typically powered by batteries, which last from several months to several years, depending on the power consumption of each end node. Here the “shelf-life” of a given sensor node is purely dependent on the lifetime of the battery. Though it is possible to simply replace the battery towards the end of the node’s life, it is not always practical to do so as the replacement itself can become an expensive “total cost of ownership."

As modern bus interface frequencies scale higher, care must be taken in the printed circuit board (PCB) layout phase of a design to ensure a robust solution.