This document describes the Tconf language coding standards. This standard describes general lexical conventions. The benefits of these coding standards include preventing namespace collisions simplifying the use of modules and improving productivity. Third-party software vendors are encouraged to follow these coding standards. These coding standards are suggested but not mandatory for third p

Voltage Mode Boost Converter Small Signal Control Loop Analysis Using the TPS61030

The GC1115 crest factor reduction (CFR) processor reduces the peak-to-average ratio (PAR) of 3G wireless signals. This application report describes how GC1115 users canconfigure the device to achieve the desired peak reduction for 3G applications. In this application report the term 3G refers both to the UMTS (3GPP) standard and to thecdma2000 (3GPP2) standards. Examples are provided for both

This application report discusses how the performance of high-speed pipeline ADCs can be optimized by designing the right clock circuitry, a good analog input network, as well as how to get the data

This reference design is intended for users designing with the TMS320C6742 TMS320C6746 TMS320C6748 OMAP-L138 or AM18x processor. Using sequenced power supplies this reference design describes a system having a 12-V input voltage and a high-efficiency dc/dc converter with ntegrated FETs and dynamic voltage and frequency scaling (DVFS) for a small simple design.Sequenced power supply archit

This application note describes how to operate the LM27961 Evaluation Module.

Digital signal processors (DSPs) typically have one or more on-chip timers that generate hardware interrupts at periodic intervals. DSP/BIOS™ normally uses one of the available on-chip timers as a source for its system clock. The on-chip timer can also be used to generate periodic hardware interrupts from the user application. DSP/BIOS also has a PRD module that allows the user to trigger pe

AN-213 Safe Operating Areas for Peripheral Drivers

ABT Ratings, Specifications and Waveforms

66AK2L06 JESD Attach to ADC12J4000/DAC38J84 Getting Started Guide /ASPH/EP Designs/TIDU963_TIDEP0034/TIDU963_TIDEP0034

The TPS5210 can generate a regulated 1.2-V output from a 12-V input. The application circuit is identical to the Application shown in the TPS5210 data sheet (SLVS171, Figure 18), except for the modifi

This document addresses questions about jitter and bit errors when used in conjunction with the Texas Instruments TLK2500IRCP serializer deserializer device.

The TivaWare Graphics Library (grlib) offers a compact yet powerful collection of graphics functions allowing the development of compelling user interfaces on small monochrome or color displays attach

Unlike regular PLLs the CDCF5801 has an extra phase aligner. Using this extra phase aligner the CDCF5801 can align two different clock phases even with differentfrequencies. Examples of where phase alignment may be useful include:· Applications where two clock buffers' outputs need to be aligned· Applications that require data synchronization with SERDES· Applications that require stati

This application report describes differences between Texas Instruments' TMS320F2802x/2803x and TMS320F2806x microcontrollers to assist in application migration. While the main focus of this document