This document descirbes implementing the Live Update application on the SAM E54 MCU with the usage of the dual bank Flash.

The CoreEDAC IP generates Error Detection And Correction (EDAC) circuitry for both internal (on-chip) and external RAM blocks. The user data is fed to the EDAC encoder, which calculates the parity bits and appends these to the user data, forming a codeword. The codeword is stored into the RAM. During user read, the read codeword is decoded first, which detects and corrects errors (if any), discards parity bits, and outputs the corrected user data word. Scrubbing periodically checks every memory location using the ECC decoder. If a location contains a corrupted word, the decoder detects and corrects the word. The scrubbing circuitry then writes the corrected word back to the same location. To provide normal access to the RAM and prevent decreasing performance, scrubbing is only done during idle periods. The scrubbing circuitry sets a proper write address and write enable signals, writing the corrected codeword back to the RAM. Writeback occurs only upon detecting an error.

This document is intended to guide MPLAB Harmony v2 users on how to develop applications using MPLAB Harmony V3.

This document contains information with respect to the software simulations of the XAUI protocol.

This application note demonstrates how to implement a basic RTG4 Field Programmable Gate Array (FPGA) fabric design using SmartDesign. The design drives LEDs on the RTG4 Development Kit board with different patterns based on the state of Reset Switch (SW7), User Switch (SW2), and User Switch (SW1).

This application note explains the following concepts/systems and processes:

• Creating a Libero System-on-Chip (SoC) project
• Implementing an RTG4 fabric design with SmartDesign
• Simulating the design
• Making pin assignments, running layout, and programming the RTG4 silicon.

The dual-panel Flash on the PIC32MZ microcontroller (MCU) allows the application to implement the Live Update features. The Live Update feature is a piece of code used to program the application code (firmware) to the inactive bank in the internal Flash or non-volatile memory (NVM).

This document describes the AES implementation of the following four confidentiality modes of operation in the MPLAB® Harmony v3 framework for SAME54:

• Electronic Code Book (ECB)

• Cipher Block Chaining (CBC)

• Counter (CTR)

• Galois Counter mode (GCM)

To illustrate the benefits of SleepWalking using the Event System, a demonstrative application is provided along with this document. This application uses an ADC with a Window Monitoring feature in Standby mode for the following use cases:

• Standby mode with Interrupts (IRQ)

• Standby mode with Event System (SleepWalking)

This document also provides comparison on power consumption between these two use cases.

This application note describes the method to run the imaging and video demo using the PolarFire SoC video kit, a dual camera sensor module, and an HDMI monitor. This solution is developed on Microchip’s PolarFire SoC video kit, which features an MPFS250TS PolarFire SoC device.

Microchip LiteFast IP is a scalable, lightweight in terms of utilization, high data-rate protocol for applications based upon high-speed serial communication. LiteFast has an in-built flow control scheme, and the physical link is maintained when there is no application data for transmission.

Common Public Radio Interface (CPRI) is an industry standard which defines the publicly available specification for the key internal interface of radio base stations between Radio Equipment Control (REC) and Radio Equipment (RE). Microchip provides the CPRI slave IP core that implements the transmitter and receiver interfaces of the CPRI standard.

Microchip offers the Mi-V processor IP and software toolchain free of cost to develop RISC-V processor-based designs. RISC-V, a standard open Instruction Set Architecture (ISA) under the governance of the RISC-V foundation, offers numerous benefits, which include enabling the open source community to test and improve cores at a faster pace than closed ISAs.

PolarFire FPGAs support Mi-V soft processors to run user applications. The objective of the application notes is to build a Mi-V processor subsystem that can execute an application from the designated fabric RAMs initialised from the sNVM/SPI Flash. The application notes also describe how to build a RISC-V application using SoftConsole and run it on a PolarFire Evaluation Board.