450 MHz TO 6000 MHz Crest Factor Detector Features: True rms response detector Envelope peak hold output Excellent temperature stability ±0.25 dB rms detection accuracy vs. temperature ±0.25 dB envelope detection accuracy vs. temperature; over the top 25 dB of the input range Over 35 dB input power dynamic range, inclusive of crest factor RF bandwidths from 450 MHz to 6 GHz Envelope bandwidths of 10 MHz 500 Ω input impedance Single-supply operation: 2.5 V to 3.3 V Low power: 3 mA at 3 V supply RoHS compliant part

Precision, 20 MHz, CMOS, Rail-to-Rail Input/Output Operational Amplifiers

General-Purpose, 55C to +125C, Wide Bandwidth, DC-Coupled VGA Features: Low noise Voltage noise: 3 nV/√Hz Current noise: 3 pA/√Hz Small-signal BW: 115 MHz Large-signal BW: 2 V p-p = 80 MHz Slew rate: 550 V/μs, 2 V p-p Gain ranges (specified) −14 dB to +46 dB 0 dB to 60 dB Gain scaling: 50 dB/V DC-coupled Single-ended input and output Supplies: ±3 V to ±12 V Temperature range: −55°C to +125°C Power 150 mW at ±3 V, −55°C < T < +125°C 84 mW at ±3 V, PWRA = 3 V

2300 MHz to 3000 MHz Quadrature Modulator

16-Bit, 100 kSPS, Single-Ended PulSAR ADC in MSOP/QFN

DSP Microcomputer

ADSP-2115 - DSP MicroComputer, 16-Bit

Internet Gateway Processor

ADSP-2171 - DSP MicroComputer, 16-Bit

Complete, Dual, 12-Bit, Serial Input, Unipolar/Bipolar, Voltage Output DAC Features:Complete, dual, 12-/14-/16-bit digital-to-analog converter (DAC)Operates from single/dual suppliesSoftware programmable output range+5 V, +10 V, +10.8 V, 5 V, 10 V, 10.8 VINL error: 16 LSB maximum, DNL error: 1 LSB maximumTotal unadjusted error (TUE): 0.1% FSR maximumSettling time: 10 s typicalIntegrated reference: 5 ppm/C maximumIntegrated reference buffersOutput control during power-up/brownoutSimultaneous updating via LDACAsynchronous CLR to zero scale or midscaleSee data sheet for additional features

Complete, Dual, 16-Bit, Serial Input, Unipolar/Bipolar, Voltage Output DAC Features: Complete, dual, 12-/14-/16-bit digital-to-analog converter (DAC) Operates from single/dual supplies Software programmable output range +5 V, +10 V, +10.8 V, ±5 V, ±10 V, ±10.8 V Total unadjusted error (TUE): 0.1% FSR maximum Settling time: 10 μs typical INL error: ±16 LSB maximum, DNL error: ±1 LSB maximum Integrated reference: 5 ppm/°C maximum Integrated reference buffers Output control during power-up/brownout Simultaneous updating via LDAC Asynchronous CLR to zero scale or midscale See data sheet for additional features

6-Output Clock Generator with Integrated 2.2 GHz VCO

High Resolution 6 GHz Fractional-N Frequency Synthesizer Features: RF bandwidth to 6 GHz 25-bit fixed modulus allows subhertz frequency resolution 2.7 V to 3.3 V power supply Separate VP allows extended tuning voltage Programmable charge pump currents 3-wire serial interface Digital lock detect Power-down mode Pin compatible with the following frequency synthesizers: ADF4110/ADF4111/ADF4112/ADF4113 ADF4106/ADF4153/ADF4154/ADF4156 Cycle slip reduction for faster lock times

Ultralow Distortion IF VGA

Fully Accurate, Quad, 16-Bit, Buffered VOUT, 4.5 V to 5.5 V nanoDAC with SPI Interface Features: Low power quad 12-/14-/16-bit DAC, ±1 LSB INL Pin compatible and performance upgrade to AD5666 Individual and common voltage reference pin options Rail-to-rail operation 4.5 V to 5.5 V power supply Power-on reset to zero scale or midscale 3 power-down functions and per-channel power-down Hardware LDAC with software LDAC override function CLR function to programmable code SDO daisy-chaining option 14-/16-lead TSSOP Internal reference buffer and internal output amplifier 

Fully Accurate, Quad, 16-Bit, Buffered VOUT, 4.5 V to 5.5 V nanoDAC with SPI Interface Features: Low power quad 12-/14-/16-bit DAC, ±1 LSB INL Pin compatible and performance upgrade to AD5666 Individual and common voltage reference pin options Rail-to-rail operation 4.5 V to 5.5 V power supply Power-on reset to zero scale or midscale 3 power-down functions and per-channel power-down Hardware LDAC with software LDAC override function CLR function to programmable code SDO daisy-chaining option 14-/16-lead TSSOP Internal reference buffer and internal output amplifier 

Octal LNA/VGA/AAF/ADC and Crosspoint Switch Features: 8 channels of LNA, VGA, AAF, and ADC Low noise preamplifier (LNA)  Input-referred noise = 1.1 nV/√Hz @ 5 MHz typical, gain = 18 dB  SPI-programmable gain = 14 dB/15.6 dB/18 dB  Single-ended input; VIN maximum = 400 mVP-P/333 mV p-p/250 mVP-P Dual-mode active input impedance matching  Bandwidth (BW) > 70 MHz  Full-scale (FS) output = 2 VP-P differential Variable gain amplifier (VGA)  Gain range = −6 dB to +24 dB  Linear-in-dB gain control Antialiasing filter (AAF)  3rd-order Butterworth cutoff  Programmable from 8 MHz to 18 MHz See Data Sheet for Additional Information

300 MHz to 4000 MHz Quadrature Modulator

14-Output Clock Generator with Integrated 2.5 GHz VCO Features: Low phase noise, phase-locked loop (PLL) On-chip VCO tunes from 2.30 GHz to 2.65 GHz External VCO/VCXO to 2.4 GHz optional 1 differential or 2 single-ended reference inputs Reference monitoring capability Automatic synchronization of all outputs on power-up 4 pairs of 800 MHz LVDS clock outputs Each output pair shares two cascaded 1-to-32 dividers with coarse phase delay Additive output jitter: 275 fs rms Fine delay adjust (Δt) on each LVDS output See datasheet for additional features

Hot-Swappable, Dual I2C Isolators, 5 Kv