Digitally Programmable Sensor Signal Amplifier Features: Very low offset voltage: 12 μV maximum over temperature  Very low input offset voltage drift:  65 nV/°C maximum High CMRR: 96 dB minimum  Digitally programmable gain and output offset voltage  Gain range from 28 to 1300  Single-wire serial interface  Stable with any capacitive load  SOIC and LFCSP packages  2.7 V to 5.5 V operation  Qualified for automotive applications

Precision, 20 MHz, CMOS, Rail-to-Rail Input/Output Operational Amplifiers

2300 MHz to 3000 MHz Quadrature Modulator

OP AMP 1MHZ 3V/uS TO-99-8; No. of Amplifiers:1 Amplifier; Bandwidth:1MHz; Slew Rate:3V/ s; Supply Voltage Range: 5V to 18V; Amplifier Case Style:TO-99; No. of Pins:8Pins; Operating Temperature Min:0 C; Packaging:Each ;RoHS Compliant: No

Precision Dual-Channel, Difference Amplifier

SUPER Sequencer with OPEN-LOOP Margining DAC

Super Sequencer with Open-Loop Margining DACs

Low Noise, Precision, 16 V, CMOS, Rail-to-Rail Operational Amplifiers

ADC, Successive Approximation, 16-Bit, 1 Func, 1 Channel, Serial Access, CMOS, PDSO8

DSP Microcomputer

DSP Microcomputer

ADSP21xx , DSP MicroComputer, 16-Bit

ADSP-2100 Family DSP Microcomputers

ADSP-2111 - DSP MicroComputer, 16-Bit

Dual 12-/14-/16-Bit, LVDS Interface, 500 MSPS DACs

High Bandwidth, Bidirectional 65 V Difference Amplifier

Complete, Dual, 12-/14-/16-Bit, Serial Input, Unipolar/Bipolar, Voltage Output DACs

6-Output Clock Generator with Integrated 2.0 GHz VCO

6-OUTPUT CLOCK GENERATOR WITH 2.8GHZ; Silicon Manufacturer:Analog Devices; Silicon Core Number:AD9518-1; Kit Application Type:Clock & Timing; Application Sub Type:PLL Clock Synthesizer; Kit Contents:Eval Board AD9518-1; Product Range:AD9518-1 Series; SVHC:No SVHC (20-Jun-2016); Features:Automatic Synchronization of All O/P on Power-up Manual O/P Synchronization Available

12-Output Clock Generator with Integrated 2.8 GHz VCO Features: Low phase noise, phase-locked loop (PLL) On-chip VCO tunes from 2.55 GHz to 2.95 GHz External VCO/VCXO to 2.4 GHz optional 1 differential or 2 single-ended reference inputs Reference monitoring capability Automatic revertive and manual reference switchover/holdover modes 2 pairs of 1.6 GHz LVPECL outputs Each output pair shares a 1-to-32 divider with coarse phase delay Additive output jitter: 225 fs rms Channel-to-channel skew paired outputs of <10 ps Accepts LVPECL, LVDS, or CMOS references to 250 MHz Programmable delays in path to PFD Digital or analog lock detect, selectable 2 pairs of 800 MHz LVDS clock outputs Each output pair shares two cascaded 1-to-32 dividers with coarse phase delay Additive output jitter: 275 fs rms Fine delay adjust (Δt) on each LVDS output Each LVDS output can be reconfigured as two 250 MHz CMOS outputs Automatic synchronization of all outputs on power-up Manual output synchronization available See datasheet for additional features