ADBF608 - Blackfin Dual Core

ADSP-BF518W-02 - BLACKFIN 400MHZ PROCESSOR

Ultrafast SiGe Voltage Comparator (Featuring Reduced Swing NECL Output Drivers) Features: 180 ps propagation delay 25 ps overdrive and slew rate dispersion 8 GHz equivalent input rise time bandwidth 100 ps minimum pulse width 37 ps typical output rise/fall 10 ps deterministic jitter (DJ) 200 fs random jitter (RJ) −2 V to +3 V input range with +5 V/−5 V supplies On-chip terminations at both input pins Resistor-programmable hysteresis Differential latch control Power supply rejection > 70 dB

Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery Features: Automatic Disconnect of SDA/SCL Lines when Bus is Stuck Low for ≥30ms Fault Flag for Stuck Bus Recovers Stuck Busses with Automatic Clocking* Bidirectional Buffer* for SDA and SCL Lines Increases Fanout Prevents SDA and SCL Corruption During Live Board Insertion and Removal from Backplane Allows Bus Pullup Voltages Above and Below VCC ±15kV Human Body Model ESD Protection Isolates Input SDA and SCL Lines from Output Compatible with I2C™, I2C Fast-Mode and SMBus Standards (Up to 400kHz Operation) READY Open Drain Output 1V Precharge on All SDA and SCL Lines High Impedance SDA, SCL Pins for VCC = 0V ENABLE Gates Connection from Input to Output MSOP 10-Pin and DFN (3mm × 3mm) Packages

Negative Voltage Hot Swap Controllers with ADC and IC Monitoring Features:Allows Safe Insertion into Live –48V Backplanes10-Bit ADC Monitors Current and VoltagesI2C/SMBus Interface or Single-Wire Broadcast ModeFloating Topology Allows Very High Voltage OperationIndependently Adjustable Inrush and Overcurrent LimitsControlled Soft-Start InrushAdjustable UV/OV Thresholds and HysteresisSequenced Power Good Outputs with DelaysAdjustable Power Good Input TimeoutProgrammable Latchoff or Auto-Retry After FaultsAlerts Host After FaultsAvailable in 28-Lead Narrow SSOP and 24-Lead (4mm × 5mm) QFN Packages

High Voltage, High-Side Current Sense Amplifier in SOT-23 Features: Supply Range: 5V to 100V, 105V Absolute Maximum (LTC6101HV) 4V to 60V, 70V Absolute Maximum (LTC6101) Low Offset Voltage: 300μV Max Fast Response: 1μs Response Time (0V to 2.5V on a 5V Output Step) Gain Configurable with 2 Resistors Low Input Bias Current: 170nA Max PSRR: 118dB Min Output Current: 1mA Max Low Supply Current: 250μA, VS = 12V Specifi ed Temperature Range: –40°C to 125°C Operating Temperature Range: –55°C to 125°C Low Profi le (1mm) SOT-23 (ThinSOT™) Package

High Performance ISM Band ASK/FSK Transmitter IC Features: Single-chip, Low-power UHK Transmitter 369.5 MHz to 395.9 MHz Frequency Operation using Fractional-N PLL and Fully-integrated VCO 3.0 V Supply Voltage Data Rates Supported < 20 kbps Low Current Consumption: 26mA at 12dBm Output at 384 MHz Power-down Mode (<1µA) 24-Lead TSSOP Package

60 Ohm, Quad SPST Switch Features: 44 V Supply Maximum Rating ±15 V Analog Signal Range Low RON (60Ω) Low Leakage (0.5nA) Break-Before-Make Switching Action Extended Plastic Temperature Range (-40ºC to +85ºC) Low Power Dissipation (33 mW) TTL/CMOS Compatible Superior Second Source for DG201A/HI201 16-Lead DIP/SOIC PackagesADG201A-EP supports defense and aerospace applications (AQEC standard) Download ADG201A-EP data sheet (pdf) Military temperature range: −55°C to +125°C Controlled manufacturing baseline One assembly and test site One fabrication site Enhanced product change notification Qualification data available on request V62/12638 DSCC Drawing Number

Single, Integer-N 550 MHz PLL Features: ADF4116: 550 MHz ADF4117: 1.2 GHz ADF4118: 3.0 GHz 2.7 V to 5.5 V power supply Separate VP allows extended tuning voltage in 3 V systems Y Grade: −40°C to +125°C Dual-modulus prescaler ADF4116: 8/9 ADF4117/ADF4118: 32/33 3-wire serial interface Digital lock detect Power-down mode Fastlock mode

AD8631 - Op Amp General Purpose 5MHz

12 Channel, 8-Bit TrimDACs with Power Shutdown & Separate VREFL Input Features: Low Cost Replaces 12 Potentiometers Individually Programmable Outputs Power Shutdown < 55 µWatts Including IDD & IREF 3-Wire SPI Compatible Serial Input Midscale Preset, AD8802 Separate VREF Range Settling, AD8804 +3 to +5 Single Supply Operation

14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Analog-to-Digital Converter Features: 1.8 V analog supply operation 1.8 V to 3.3 V output supply SNR = 71.7 dBc (72.7 dBFS) to 70 MHz input SFDR = 85 dBc to 70 MHz input Low power: 395 mW @ 125 MSPS Differential input with 650 MHz bandwidth On-chip voltage reference and sample-and-hold amplifier DNL = ±0.4 LSB Flexible analog input: 1 V p-p to 2 V p-p range Offset binary, Gray code, or twos complement data format Data output clock and clock duty cycle stabilizer Serial port control Built-in selectable digital test pattern generation Programmable clock and data alignment

14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Analog-to-Digital Converter Features: 1.8 V analog supply operation 1.8 V to 3.3 V output supply SNR = 71.7 dBc (72.7 dBFS) to 70 MHz input SFDR = 85 dBc to 70 MHz input Low power: 395 mW @ 125 MSPS Differential input with 650 MHz bandwidth On-chip voltage reference and sample-and-hold amplifier DNL = ±0.4 LSB Flexible analog input: 1 V p-p to 2 V p-p range Offset binary, Gray code, or twos complement data format Data output clock and clock duty cycle stabilizer Serial port control Built-in selectable digital test pattern generation Programmable clock and data alignment

Octal LNA/VGA/AAF/ADC and Crosspoint Switch Features: 8 channels of LNA, VGA, AAF, and ADC Low noise preamplifier (LNA) - See data sheet for additional information Variable gain amplifier (VGA) - See data sheet for additional information Antialiasing filter (AAF) - See data sheet for additional information Analog-to-digital converter (ADC) - See data sheet for additional information Includes an 8 × 8 differential crosspoint switch to support continuous wave (CW) Doppler Low power, 195 mW per channel at 12 bits/40 MSPS (TGC) See data sheet for additional features

8-Bit, 50 MSPS/80 MSPS/100 MSPS ADC Features: Low Power: 90 mW at 100 MSPS On-Chip Reference and Track/Hold 475 MHz Analog Bandwidth 46.5 dB SNR at 100 MSPS with 41 MHz input 1 Vp-p Analog Input Range Single +3.0 V Supply Operation (2.7 -3.6 V) Power Down Mode: 4.2 mW

Ethernet/Gigabit Ethernet Clock Generator Features: Redundant input reference clock capability Reference monitoring function Fully integrated VCO/PLL core Jitter (rms) 0.234 ps rms jitter (10 kHz to 10 MHz) at 156.25 MHz 0.243 ps rms jitter (12 kHz to 20 MHz) at 156.25 MHz Input frequency: 19.44 MHz or 25 MHz Preset frequency translations Using a 19.44 MHz input reference 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz Using a 25 MHz input reference 25 MHz, 33.33 MHz, 50 MHz, 66.67 MHz, 80 MHz, 100 MHz, 125 MHz, 133.3 MHz, 156.25 MHz, 160 MHz, 312.5 MHz Output drive formats: HSTL, LVDS, HCSL, and 1.8 V and 3.3 V CMOS Integrated loop filter (requires a single external capacitor) 2 copies of reference clock output Device configuration via strapping pins (PPRx) Space-saving 7 mm × 7 mm 48-lead LFCSP 3.3 V operation

16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) Features: 1.8 V analog supply operation 1.8 V CMOS or LVDS output supply SNR 82 dBFS at 30 MHz input and 105 MSPS data rate 83 dBFS at 9.7 MHz input and 25 MSPS data rate SFDR 90 dBc at 30 MHz input and 105 MSPS data rate 95 dBc at 9.7 MHz input and 25 MSPS data rate Low power 328 mW per channel at 105 MSPS 119 mW per channel at 25 MSPS Integer 1-to-8 input clock divider See data sheet for additional featuresAD9650-EP supports defense and aerospace applications (AQEC standard) Download AD9650-EP data sheet (pdf)

10-Bit, 100 MSPS+ TxDAC D/A Converter Features: Member of Pin-Compatible TxDAC Product Family 125 MSPS Update Rate 10-Bit Resolution Excellent Spurious Free Dynamic Range Performance SFDR to Nyquist @ 40 MHz Output: 52 dBc Differential Current Outputs: 2 ma to 20 mA Edge-Triggered Latches See datasheet for additional features

16-Bit 160 MSPS 2x/4x/8x Interpolating Dual TxDAC+ D/A Converter Features: 16-bit resolution, 160 MSPS/400 MSPS input/output data rate Selectable 2×/4×/8× interpolating filter Programmable channel gain and offset adjustment fS/4, fS/8 digital quadrature modulation capability Fully compatible SPI® port Direct IF transmission mode for 70 MHz + IFs Enables image rejection architecture See datasheet for additional features

Dual, 12-Bit, 1 GSPS, Digital-to-Analog Converter Features: Low power: 1.0 W @ 1 GSPS, 600 mW @ 500 MSPS, full operating conditions Single carrier W-CDMA ACLR = 80 dBc @ 80 MHz IF Analog output: adjustable 8.7 mA to 31.7 mA, RL = 25 Ω to 50 Ω Novel 2×, 4×, and 8× interpolator/coarse complex modulator allows carrier placement anywhere in DAC bandwidth Auxiliary DACs allow control of external VGA and offset control Multiple chip synchronization interface High performance, low noise PLL clock multiplier Digital inverse sinc filter 100-lead, exposed paddle TQFP