The HMC666LP4(E) is a high dynamic range passive MMIC mixer with integrated LO amplifier in a 4x4 SMT QFN package covering 3.1 - 3.9 GHz. Excellent input IP3 performance of +31 dBm for down conversion is provided for WiMAX and fixed wireless applications at an LO drive of 0 dBm. The LO port is optimized for low side LO applications.With an input 1 dB compression of +23 dBm, the RF port will accept a wide range of input signal levels. Conversion loss is 9 dB typical. The DC to 800 MHz IF frequency response will satisfy WiMAX transmit or receive frequency plans. The HMC666LP4(E) is pin for pin compatible with the HMC688LP4(E) which is a 2.0 - 2.7 GHz mixer with LO amplifier.APPLICATIONS WiMAX/4G & Fixed Wireless Infrastructure & Repeaters Transmitters & Receivers Test & Measurement Equipment

HMC750 is a limiting amplifier designed to support data transmission rates up to 12.5 Gbps. The amplifier can operate over a wide range of input voltage levels and provides constant-level differential output swing. HMC750 also features an output level control pin, VC1, which allows for loss compensation or for signal level optimization. Differential output signal swing can be adjustable up to 880 mVp-p. Input signals higher than 3 mVp-p can be amplified to saturated 880 mVp-p differential signal.All single-ended input signals to the HMC750 are terminated with 50 ohms to +5V on-chip, and may be either AC or DC coupled. The outputs of the HMC750 may be operated either differentially or single-ended. Outputs can be connected directly to a 50 ohm terminated system referenced to +5V, while DC blocking capacitors may be used if the terminating system is 50 ??to a non +5V voltage. The HMC750 operates from a single +5V DC supply and is available in a plastic RoHS compliant 4?4 mm SMT package.APPLICATIONS OC-192 Receivers 10 Gbps Ethernet Receivers 10 Gbps Fiber Channel Receivers Broadband Test & Measurement

The HMC726 is an AND/NAND/OR/NOR function designed to support data transmission rates of up to 13 Gbps, and clock frequencies as high as 13 GHz. The HMC726 may be easily configured to provide any of the following logic functions: AND, NAND, OR and NOR. All input signals to the HMC726 are terminated with 50 Ohms to ground on-chip, and maybe either AC or DC coupled.The differential outputs of the HMC726 may be either AC or DC coupled. Outputs can be connected directly to a 50 Ohm to ground terminated system, while DC blocking capacitors may be used if the terminating system is 50 Ohms to a non-ground DC voltage. The HMC726 operates from a single -3.3V DC supply, dissipates only 230 mW, and is available in a ceramic RoHS compliant 3?3 mm SMT package.APPLICATIONS RF ATE Applications Broadband Test & Measurement Serial Data Transmission?up to 13 Gbps Digital Logic Systems up to 13 GHz

The HMC728 is a 2:1 Selector designed to support data transmission rates of up to 13 Gbps, and selector port operation of up to 13 GHz. The selector routes one of the two single-ended inputs to the differential output upon assertion of the proper select port. All single-ended input signals to the HMC728 are terminated with 50 ohms to ground on-chip, and may be either AC or DC coupled.The outputs of the HMC728 may be operated either differentially or single-ended. Outputs can be connected directly to a 50 ohm terminated system, while DC blocking capacitors may be used if the terminating system is 50 ohms to a non-ground DC voltage. The HMC728 operates from a single -3.3V DC supply and is available in a ceramic RoHS compliant 3x3 mm SMT package.APPLICATIONS 2:1 Multiplexer up to 13 Gbps F ATE Applications Broadband Test & Measurement Serial Data Transmission up to 13 Gbps Redundant Path Switching Built-in Test

The HMC752LC4 is a GaAs MMIC Low Noise WidebandAmplifier housed in a leadless 4x4 mm ceramicsurface mount package. The amplifier operates between24 and 28 GHz, providing up to 25 dB of smallsignal gain, 2.5 dB noise figure, and output IP3 of+26 dBm, while requiring only 70 mA from a +3V supply.The P1dB output power of up to +13 dBm enablesthe LNA to function as a LO driver for balanced, I/Qor image reject mixers. The HMC752LC4 also featuresI/Os that are DC blocked and internally matched to50 Ohms, making it ideal for high capacity microwaveradios or VSAT applications.Applications Point-to-Point Radios Point-to-Multi-Point Radios Military & Space Test Instrumentation

The HMC736 is a GaAs InGaP Heterojunction Bipolar Transistor (HBT) MMIC VCO. The HMC736 integrates a resonator, negative resistance device, varactor diode and feature half frequency output. The VCO's phase noise performance is excellent over temperature, shock, and process due to the oscillator's monolithic structure. Power output is +9 dBm typical from a +4.2V supply voltage. The voltage controlled oscillator is packaged in a leadless QFN 4?4 mm surface mount package, and requires no external matching components.APPLICATIONS Point-to-Multi-Point Radios Test Equipment & Industrial Controls SATCOM Military End-Use

The HMC785LP4E is a high dynamic range passive MMIC mixer with integrated LO amplifier in a 4x4 SMT QFN package covering 1.7 to 2.2 GHz. Excellent input IP3 performance of +38 dBm for down conversion is provided for 3G & 4G GSM/CDMA applications at an LO drive of 0 dBm. With an input 1 dB compression of +26 dBm, the RF port will accept a wide range of input signal levels. Conversion loss is 8 dB typical. Up to 300 MHz IF frequency response will satisfy GSM/CDMA transmit or receive frequency plans. The HMC785LP4E is optimized for low side LO frequency plans for 1.7 - 2.2 GHz RF Band and is pin for pin compatible with the HMC685LP4E.APPLICATIONS Cellular/3G & LTE/WiMAX/4G Basestations & Repeaters GSM, CDMA & OFDM Transmitters and Receivers

The HMC821LP6CE is a fully functioned Fractional-N Phase-Locked-Loop (PLL) Frequency Synthesizer with an Integrated Voltage Controlled Oscillator (VCO). The synthesizer consists of an integrated low noise VCO with a triband output, an autocalibration subsystem for low voltage VCO tuning, a very low noise digital Phase Detector (PD), a precision controlled charge pump, a low noise reference path divider and a fractional divider.The fractional synthesizer features an advanced delta-sigma modulator design that allows both ultra-fine step sizes and low spurious products. The phase detector (PD) features cycle slip prevention (CSP) technology to allow faster frequency hopping times. Ultra low in-close phase noise and low spurious also allows wider loop bandwidths for faster frequency hopping and low micro-phonics.For theory of operation and register map refer to the 'PLLs with Integrated VCO - RF VCOs' Operating Guide.Applications Cellular/4G Infrastructure Repeaters and Femtocells Communications Test Equipment CATV Equipment Phased Array Applications DDS Replacement? Very High Data Rate Radios

The HMC824LP6CE is a fully functioned Fractional-N Phase-Locked-Loop (PLL) Frequency Synthesizer with an Integrated Voltage Controlled Oscillator (VCO). The synthesizer consists of an integrated low noise VCO with divide-by-2 output, an autocalibration subsystem for low voltage VCO tuning, a very low noise digital Phase Detector (PD), a precision controlled charge pump, a low noise reference path divider and a fractional divider.The fractional synthesizer features an advanced delta-sigma modulator design that allows both ultra-fine step sizes and low spurious products. The phase detector (PD) features cycle slip prevention (CSP) technology to allow faster frequency hopping times. Ultra low in-close phase noise and low spurious also allows wider loop bandwidths for faster frequency hopping and low micro-phonics.For theory of operation and register map refer to the 'PLLs with Integrated VCO - RF VCOs' Operating Guide.Applications Cellular/4G Infrastructure Repeaters and Femtocells Communications Test Equipment CATV Equipment Phased Array Applications DDS Replacement? Very High Data Rate Radios

The HMC826LP6CE is a fully functioned Fractional-N Phase-Locked-Loop (PLL) Frequency Synthesizer with an Integrated Voltage Controlled Oscillator (VCO). The synthesizer consists of an integrated low noise VCO with divide-by-2 output, an autocalibration subsystem for low voltage VCO tuning, a very low noise digital Phase Detector (PD), a precision controlled charge pump, a low noise reference path divider and a fractional divider.The fractional synthesizer features an advanced delta-sigma modulator design that allows both ultra-fine step sizes and low spurious products. The phase detector (PD) features cycle slip prevention (CSP) technology to allow faster frequency hopping times. Ultra low in-close phase noise and low spurious also allows wider loop bandwidths for faster frequency hopping and low micro-phonics.For theory of operation and register map refer to the 'PLLs with Integrated VCO - RF VCOs' Operating Guide.Applications Cellular/4G Infrastructure Repeaters and Femtocells Communications Test Equipment CATV Equipment Phased Array Applications DDS Replacement? Very High Data Rate Radios

The HMC831LP6CE is a fully functioned Fractional-N Phase-Locked-Loop (PLL) Frequency Synthesizer with an Integrated Voltage Controlled Oscillator (VCO). The synthesizer consists of an integrated low noise VCO, an autocalibration subsystem for low voltage VCO tuning, a very low noise digital Phase Detector (PD), a precision controlled charge pump, a low noise reference path divider and a fractional divider.The fractional synthesizer features an advanced delta-sigma modulator design that allows both ultra-fine step sizes and low spurious products. The phase detector (PD) features cycle slip prevention (CSP) technology to allow faster frequency hopping times. Ultra low in-close phase noise and low spurious also allows wider loop bandwidths for faster frequency hopping and low micro-phonics.For theory of operation and register map refer to the 'PLLs with Integrated VCO - RF VCOs' Operating Guide.Applications Cellular/4G Infrastructure Repeaters and Femtocells Communications Test Equipment CATV Equipment Phased Array Applications DDS Replacement? Very High Data Rate Radios

The HMC839LP6CE is a fully functioned Fractional-N Phase-Locked-Loop (PLL) Frequency Synthesizer with an Integrated Voltage Controlled Oscillator (VCO). The synthesizer consists of an integrated low noise VCO with a triband output, an autocalibration subsystem for low voltage VCO tuning, a very low noise digital Phase Detector (PD), a precision controlled charge pump, a low noise reference path divider and a fractional divider.The fractional synthesizer features an advanced delta-sigma modulator design that allows both ultra-fine step sizes and low spurious products. The phase detector (PD) features cycle slip prevention (CSP) technology to allow faster frequency hopping times. Ultra low in-close phase noise and low spurious also allows wider loop bandwidths for faster frequency hopping and low micro-phonics.For theory of operation and register map refer to the 'PLLs with Integrated VCO - RF VCOs' Operating Guide.Applications Cellular/4G Infrastructure Repeaters and Femtocells Communications Test Equipment CATV Equipment Phased Array Applications DDS Replacement? Very High Data Rate Radios

The HMC840LP6CE is a fully functioned Fractional-N Phase-Locked-Loop (PLL) Frequency Synthesizer with an Integrated Voltage Controlled Oscillator (VCO). The synthesizer consists of an integrated low noise VCO with a triband output, an autocalibration subsystem for low voltage VCO tuning, a very low noise digital Phase Detector (PD), a precision controlled charge pump, a low noise reference path divider and a fractional divider.The fractional synthesizer features an advanced delta-sigma modulator design that allows both ultra-fine step sizes and low spurious products. The phase detector (PD) features cycle slip prevention (CSP) technology to allow faster frequency hopping times. Ultra low in-close phase noise and low spurious also allows wider loop bandwidths for faster frequency hopping and low micro-phonics.For theory of operation and register map refer to the 'PLLs with Integrated VCO - RF VCOs' Operating Guide.Applications Cellular/4G Infrastructure Repeaters & Femtocells Communications?Test Equipment CATV Equipment Phased Array Applications DDS Replacement? Very High Data Rate Radios

The HMC900LP5E is a 6th order, programmable bandwidth, fully calibrated, dual low pass filter. It features 0 or 10 dB input gain setting and supports arbitrary bandwidths from 3.5 to 50 MHz, and when calibrated, is accurate to ?2.5% of the desired bandwidth. It includes a filter bypass option with a bandwidth of 100 MHz, while retaining gain and common mode settings.Housed in a compact 5x5mm SMT QFN package, the HMC900LP5E requires minimal external components and provides a low cost alternative to more complicated switched discrete filter architectures. Filter calibration for the HMC900LP5E is accomplished with any reference clock rate from 20 to 80 MHz. One time programmable (OTP) memory offers unsurpassed flexibility allowing the user 'set and forget' parameters like gain, and bandwidth setting.Matched filter paths provide excellent quadrature balance, making the HMC900LP5E ideal for I/Q communications applications. The 6th order Butterworth transfer function delivers superior stop band rejection while maintaining both a flat passband and minimal group delay variation.Applications Baseband Filtering for A/D or?D/A Converters? Point-to-Point, Fixed Wireless &?Cellular Base Station Transceivers Integrated Direct Conversion Receiver (DCR)? Software Defined Radio Applications Test & Measurement Equipment

The HMC966LP4E is a compact GaAs MMIC I/Q downconverter in a leadless RoHS compliant SM T package. This device provides a small signal conversion gain of 12 dB with a noise figure of 2.5 dB and 40 dBc of image rejection across the frequency band. The HMC966LP4E utilizes an LNA followed by an image reject mixer which is driven by an active x2 multiplier. The image reject mixer eliminates the need for a filter following the LNA, and removes thermal noise at the image frequency. I and Q mixer outputs are provided and an external 90? hybrid is needed to select the required sideband. The HMC966LP4E is a much smaller alternative to hybrid style image reject mixer downconverter assemblies, and is compatible with surface mount manufacturing techniques.Applications Point-to-Point &?Point-to-Multi-Point Radio Military Radar, EW & ELINT Satellite Communications

The HMC858LC4B is a 2:1 Selector designed to sup-port data transmission rates of up to 14 Gbps, and selector port operation of up to 14 GHz. The selector routes one of the two differential inputs to the differential output upon assertion of the proper select port. The HMC858LC4B also features an output level control pin, VR, which allows for loss compensation or for signal level optimization.All differential input signals to the HMC858LC4B are terminated with 50 ohms to ground on-chip, and may be either AC or DC coupled. The outputs of the HMC858LC4B may be operated either differentially or single-ended. Outputs can be connected directly to a 50 ohm terminated system, while DC blocking capacitors may be used if the terminating system is 50 ohms to a non-ground DC voltage. The HMC858LC4B operates from a single -3.3V DC supply and is available in a ceramic RoHS-compliant, 4?4 mm SMT package.APPLICATIONS 2:1 Multiplexer up to 14 Gbps 16G Fiber Channel Serial Data Transmission?up to 14 Gbps Redundant Path Switching Built-in Test Broadband Test & Measurement

The AD633 is a functionally complete, four-quadrant, analog multiplier. It includes high impedance, differential X and Y inputs, and a high impedance summing input (Z). The low impedance output voltage is a nominal 10 V full scale provided by a buried Zener. The AD633 is the first product to offer these features in modestly priced 8-lead PDIP and SOIC packages.The AD633 is laser calibrated to a guaranteed total accuracy of 2% of full scale. Nonlinearity for the Y input is typically less than 0.1% and noise referred to the output is typically less than 100 ?V rms in a 10 Hz to 10 kHz bandwidth. A 1 MHz bandwidth, 20 V/?s slew rate, and the ability to drive capacitive loads make the AD633 useful in a wide variety of applications where simplicity and cost are key concerns.The versatility of the AD633 is not compromised by its simplicity. The Z input provides access to the output buffer amplifier, enabling the user to sum the outputs of two or more multipliers, increase the multiplier gain, convert the output voltage to a current, and configure a variety of applications.The AD633 is available in 8-lead PDIP and SOIC packages. It is specified to operate over the 0?C to 70?C commercial temperature range (J Grade) or the ?40?C to +85?C industrial temperature range (A Grade).Product Highlights The AD633 is a complete four-quadrant multiplier offered in low cost 8-lead SOIC and PDIP packages. The result is a product that is cost effective and easy to apply. No external components or expensive user calibration are required to apply the AD633. Monolithic construction and laser calibration make the device stable and reliable. High (10 M?) input resistances make signal source loading negligible. Power supply voltages can range from ?8 V to ?18 V. The internal scaling voltage is generated by a stable Zener diode; multiplier accuracy is essentially supply insensitive.Applications Multiplication, division, squaring Modulation/demodulation, phase detection Voltage-controlled amplifiers/attenuators/filters

The AD6672 is an 11-bit intermediate receiver with sampling speeds of up to 250 MSPS. The AD6672 is designed to support communications applications, where low cost, small size, wide bandwidth, and versatility are desired.The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.The ADC core output is connected internally to a noise shaping requantizer (NSR) block. The device supports two output modes that are selectable via the serial port interface (SPI). With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6672 supports enhanced SNR performance within a limited region of the Nyquist bandwidth while maintaining an 11-bit output resolution. The NSR block is programmed to provide a bandwidth of up to 33% of the sample clock. For example, with a sample clock rate of 250 MSPS, the AD6672 can achieve up to 73.6 dBFS SNR for an 82 MHz bandwidth at 185 MHz fIN.With the NSR block disabled, the ADC data is provided directly to the output with an output resolution of 11 bits. The AD6672 can achieve up to 66.6 dBFS SNR for the entire Nyquist bandwidth when operated in this mode. APPLICATIONS Communications Diversity radio and smart antenna (MIMO) systems Multimode digital receivers (3G) WCDMA, LTE, CDMA2000 WiMAX, TD-SCDMA I/Q demodulation systems General-purpose software radios

The AD6674 is a 385 MHz bandwidth mixed-signal intermediate frequency (IF) receiver. It consists of two, 14-bit 1.0 GSPS/750 MSPS/500 MSPS analog-to-digital converters (ADC) and various digital signal processing blocks consisting of four wideband DDCs, an NSR, and VDR monitoring. It has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of sampling wide bandwidth analog signals of up to 2 GHz. The AD6674 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.Applications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers

For a limited time, take a live test drive of the AD6676 by using our?remote evaluation software.The AD6676 is a highly integrated IF subsystem that candigitize radio frequency (RF) bands up to 160 MHz in widthcentered on an intermediate frequency (IF) of 70 MHz to 450 MHz. Unlike traditional Nyquist IF sampling ADCs, theAD6676 relies on a tunable band-pass ?-? ADC with a high oversampling ratio to eliminate the need for band specific IFSAW filters and gain stages, resulting in significant simplification of the wideband radio receiver architecture. On-chip quadraturedigital downconversion followed by selectable decimation filtersreduces the complex data rate to a manageable rate between 62.5 MSPS to 266.7 MSPS. The 16-bit complex output data is transferred to the host via a single or dual lane JESD204B interfacesupporting line rates of up to 5.333 Gbps.Applications Wideband cellular infrastructure equipment and repeaters? Point-to-point microwave equipment? Instrumentation? Spectrum and communication analyzers? Software defined radio