The ADRF5730 is a silicon, 6-bit digital attenuator with 31.5 dB attenuation control range in 0.5 dB steps.This device operates from 100 MHz to 40 GHz with better than 4.8 dB of insertion loss and excellent attenuation accuracy. The ADRF5730 has a radio frequency (RF) input power handling capability of 27 dBm average and 30 dBm peak for all states.The ADRF5730 requires a dual supply voltage of +3.3 V and ?3.3 V. The device features serial peripheral interface (SPI), parallel mode control, and complementary metal-oxide semiconductor (CMOS)-/low voltage transistor to transistor logic (LVTTL)-compatible controls.The ADRF5730 is pin-compatible with the ADRF5720 low frequency cutoff version, which operates from 9 kHz to 40 GHz.The ADRF5730 RF ports are designed to match a characteristic impedance of 50 ?. For wideband applications, impedance matching on the RF transmission lines can further optimize high frequency insertion loss, return loss, and attenuation accuracy characteristics. Refer to the Electrical Specifications section, the Typical Performance Characteristics section, and the Applications Information section for more details.The ADRF5730 comes in a 24-terminal, 4 mm ? 4 mm, RoHS-compliant, land grid array (LGA) package and operates from ?40?C to +105?C.Applications Industrial scanners Test and instrumentation Cellular infrastructure: 5G millimeter wave Military radios, radars, electronic counter measures (ECMs) Microwave radios and very small aperture terminals (VSATs)

The ADRF5740 is a silicon, 4-bit digital attenuator with 22 dB attenuation control range in 2 dB steps.The ADRF5740 operates from 10 MHz to 60 GHz with less than 3.3 dB of insertion loss and with ?(0.2 + 7.0% of attenuation state) of attenuation accuracy at 55 GHz. The ATTIN port of the ADRF5740 has an RF input power handling capability of 24 dBm average and 24 dBm peak for all states.The ADRF5740 requires a dual supply voltage of +3.3 V and ?3.3 V. The ADRF5740 features parallel mode control, and CMOS- and low voltage transistor to transistor logic (LVTTL)-compatible controls.The ADRF5740 RF ports are designed to match a characteristic impedance of 50 ?. The ADRF5740 comes in a 16-terminal, 2.5 mm ? 2.5 mm, RoHS compliant, land grid array (LGA) package and operates from ?40?C to +105?C.Applications Industrial scanners Test and instrumentation Cellular infrastructure: 5G millimeter wave Military radios, radars, electronic counter measures (ECMs) Microwave radios and very small aperture terminals (VSATs)

The ADRV9002 is a highly integrated RF transceiver that has dual-channel transmitters, dual-channel receivers, integrated synthesizers, and digital signal processing functions.The ADRV9002 is a high performance, highly linear, high dynamic range transceiver designed for performance vs. power consumption system optimization. The device is configurable and ideally suited to demanding, low power, portable and battery powered equipment. The ADRV9002 operates from 30 MHz to 6000 MHz and covers the UHF, VHF, industrial, scientific, and medical (ISM) bands, and cellular frequency bands in narrow-band (kHz) and wideband operation up to 40 MHz. The ADRV9002 is capable of both TDD and FDD operation.The transceiver consists of direct conversion signal paths with state-of-the-art noise figure and linearity. Each complete receiver and transmitter subsystem includes dc offset correction, quadrature error correction (QEC), and programmable digital filters, which eliminate the need for these functions in the digital baseband. In addition, several auxiliary functions, such as auxiliary analog-to-digital converters (ADCs), auxiliary digital-to-analog converters (DACs), and general-purpose inputs/outputs (GPIOs), are integrated to provide additional monitoring and control capability.The fully integrated phase-locked loops (PLLs) provide high performance, low power, fractional-N frequency synthesis for the transmitter, receiver, and clock sections. Careful design and layout techniques provide the isolation required in high performance personal radio applications. All voltage controlled oscillator (VCO) and loop filter components are integrated to minimize the external component count. The local oscillators (LOs) have flexible configuration options and include fast lock modes.The transceiver includes low power sleep and monitor modes to save power and extend the battery life of portable devices while monitoring communications.The fully integrated, low power digital predistortion (DPD) is optimized for both narrow-band and wideband signals and enables linearization of high efficiency power amplifiers.The ADRV9002 core can be powered directly from 1.0 V, 1.3 V, and 1.8 V regulators and is controlled via a standard 4-wire serial port. Other voltage supplies are used to provide proper digital interface levels and to optimize the receiver, transmitter, and auxiliary converter performance.High data rate and low data rate interfaces are supported using configurable CMOS or low voltage differential signaling (LVDS) serial synchronous interface (SSI) choice.The ADRV9002 is packaged in a 12 mm ? 12 mm, 196-ball chip scale package ball grid array (CSP_BGA).APPLICATIONS Mission critical communications Very high frequency (VHF), ultrahigh frequency (UHF), and cellular to 6 GHz Time division duplexing (TDD) and frequency division duplexing (FDD) applications

The ADRV9026 is a highly integrated, radio frequency (RF) agile transceiver offering four independently controlled transmitters, dedicated observation receiver inputs for monitoring each transmitter channel, four independently controlled receivers, integrated synthesizers, and digital signal processing functions providing a complete transceiver solution. The device provides the performance demanded by cellular infrastructure applications, such as small cell base station radios, macro 3G/4G/5G systems, and massive multiple in/multiple out (MIMO) base stations. The receiver subsystem consists of four independent, wide bandwidth, direct conversion receivers with wide dynamic range. The four independent transmitters use a direct conversion modulator resulting in low noise operation with low power consumption. The device also includes two wide bandwidth, time shared, observation path receivers with two inputs each for monitoring transmitter outputs. The complete transceiver subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. Other auxiliary functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) that provide an array of digital control options are also integrated. To achieve a high level of RF performance, the transceiver includes five fully integrated phase-locked loops (PLLs). Two PLLs provide low noise and low power fractional-N RF synthesis for the transmitter and receiver signal paths. A third fully integrated PLL supports an independent local oscillator (LO) mode for the observation receiver. The fourth PLL generates the clocks needed for the converters and digital circuits, and a fifth PLL provides the clock for the serial data interface. A multichip synchronization mechanism synchronizes the phase of all LOs and baseband clocks between multiple ADRV9026 chips. All voltage controlled oscillators (VCOs) and loop filter components are integrated and adjustable through the digital control interface. The serial data interface consists of four serializer lanes and four deserializer lanes. The interface supports both the JESD204B and JESD204C standards, operating at data rates up to 24.33 Gbps. The interface also supports interleaved mode for lower bandwidths, thus reducing the number of high speed data interface lanes to one. Both fixed and floating-point data formats are supported. The floating-point format allows internal automatic gain control (AGC) to be invisible to the demodulator device. The ADRV9026 is powered directly from 1.0 V, 1.3 V, and 1.8 V regulators and is controlled via a standard serial peripheral interface (SPI) serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9026 is packaged in a 14 mm ? 14 mm, 289-ball chip scale ball grid array (CSP_BGA).Applications 3G/4G/5G TDD and FDD massive MIMO, macro and small cell base stations

The AD9375 is a highly integrated, wideband radio frequency (RF) transceiver offering dual-channel transmitters (Tx) and receivers (Rx), integrated synthesizers, a fully integrated digital predistortion (DPD) actuator and adaptation engine, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption required by 3G/4G small cell and massive multiple input, multiple output (MIMO) equipment in both frequency division duplex (FDD) and time division duplex (TDD) applications. The AD9375 operates from 300 MHz to 6000 MHz, covering most of the licensed and unlicensed cellular bands. The DPD algorithm supports linearization on signal bandwidths up to 40 MHz depending on the power amplifier (PA) characteristics (for example, two adjacent 20 MHz carriers). The IC supports Rx bandwidths up to 100 MHz. It also supports observation receiver (ORx) and Tx synthesis bandwidths up to 250 MHz to accommodate digital correction algorithms.The transceiver consists of wideband direct conversion signal paths with state-of-the-art noise figure and linearity. Each complete Rx and Tx subsystem includes dc offset correction, quadrature error correction (QEC), and programmable digital filters, eliminating the need for these functions in the digital baseband. Several auxiliary functions such as an auxiliary analog-to-digital converter (ADC), auxiliary digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) are integrated to provide additional monitoring and control capability.An ORx channel with two inputs is included to monitor each Tx output and implement calibration applications. This channel also connects to three sniffer receiver (SnRx) inputs that can monitor radio activity in different bands.The high speed JESD204B interface supports lane rates up to 6144 Mbps. Four lanes are dedicated to the transmitters and four lanes are dedicated to the receiver and observation receiver channels.The fully integrated phase-locked loops (PLLs) provide high performance, low power, fractional-N frequency synthesis for the Tx, the Rx, the ORx, and the clock sections. Careful design and layout techniques provide the isolation demanded in high performance base station applications. All voltage controlled oscillator (VCO) and loop filter components are integrated to minimize the external component count.The device contains a fully integrated, low power DPD actuator and adaptation engine for use in PA linearization. The DPD feature enables use of high efficiency PAs, significantly reducing the power consumption of small cell base station radios while also reducing the number of JESD204B lanes necessary to interface with baseband processors.A 1.3 V supply is required to power the AD9375 core, and a standard 4-wire serial port controls it. Other voltage supplies provide proper digital interface levels and optimize transmitter and auxiliary converter performance. The AD9375 is packaged in a 12 mm ? 12 mm, 196-ball chip scale ball grid array (CSP_BGA).Applications 3G/4G small cell base stations (BTS) 3G/4G massive MIMO/active antenna systems

The AD9375 is a highly integrated, wideband radio frequency (RF) transceiver offering dual-channel transmitters (Tx) and receivers (Rx), integrated synthesizers, a fully integrated digital predistortion (DPD) actuator and adaptation engine, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption required by 3G/4G small cell and massive multiple input, multiple output (MIMO) equipment in both frequency division duplex (FDD) and time division duplex (TDD) applications. The AD9375 operates from 300 MHz to 6000 MHz, covering most of the licensed and unlicensed cellular bands. The DPD algorithm supports linearization on signal bandwidths up to 40 MHz depending on the power amplifier (PA) characteristics (for example, two adjacent 20 MHz carriers). The IC supports Rx bandwidths up to 100 MHz. It also supports observation receiver (ORx) and Tx synthesis bandwidths up to 250 MHz to accommodate digital correction algorithms.The transceiver consists of wideband direct conversion signal paths with state-of-the-art noise figure and linearity. Each complete Rx and Tx subsystem includes dc offset correction, quadrature error correction (QEC), and programmable digital filters, eliminating the need for these functions in the digital baseband. Several auxiliary functions such as an auxiliary analog-to-digital converter (ADC), auxiliary digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) are integrated to provide additional monitoring and control capability.An ORx channel with two inputs is included to monitor each Tx output and implement calibration applications. This channel also connects to three sniffer receiver (SnRx) inputs that can monitor radio activity in different bands.The high speed JESD204B interface supports lane rates up to 6144 Mbps. Four lanes are dedicated to the transmitters and four lanes are dedicated to the receiver and observation receiver channels.The fully integrated phase-locked loops (PLLs) provide high performance, low power, fractional-N frequency synthesis for the Tx, the Rx, the ORx, and the clock sections. Careful design and layout techniques provide the isolation demanded in high performance base station applications. All voltage controlled oscillator (VCO) and loop filter components are integrated to minimize the external component count.The device contains a fully integrated, low power DPD actuator and adaptation engine for use in PA linearization. The DPD feature enables use of high efficiency PAs, significantly reducing the power consumption of small cell base station radios while also reducing the number of JESD204B lanes necessary to interface with baseband processors.A 1.3 V supply is required to power the AD9375 core, and a standard 4-wire serial port controls it. Other voltage supplies provide proper digital interface levels and optimize transmitter and auxiliary converter performance. The AD9375 is packaged in a 12 mm ? 12 mm, 196-ball chip scale ball grid array (CSP_BGA).Applications 3G/4G small cell base stations (BTS) 3G/4G massive MIMO/active antenna systems

The AD9375 is a highly integrated, wideband radio frequency (RF) transceiver offering dual-channel transmitters (Tx) and receivers (Rx), integrated synthesizers, a fully integrated digital predistortion (DPD) actuator and adaptation engine, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption required by 3G/4G small cell and massive multiple input, multiple output (MIMO) equipment in both frequency division duplex (FDD) and time division duplex (TDD) applications. The AD9375 operates from 300 MHz to 6000 MHz, covering most of the licensed and unlicensed cellular bands. The DPD algorithm supports linearization on signal bandwidths up to 40 MHz depending on the power amplifier (PA) characteristics (for example, two adjacent 20 MHz carriers). The IC supports Rx bandwidths up to 100 MHz. It also supports observation receiver (ORx) and Tx synthesis bandwidths up to 250 MHz to accommodate digital correction algorithms.The transceiver consists of wideband direct conversion signal paths with state-of-the-art noise figure and linearity. Each complete Rx and Tx subsystem includes dc offset correction, quadrature error correction (QEC), and programmable digital filters, eliminating the need for these functions in the digital baseband. Several auxiliary functions such as an auxiliary analog-to-digital converter (ADC), auxiliary digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) are integrated to provide additional monitoring and control capability.An ORx channel with two inputs is included to monitor each Tx output and implement calibration applications. This channel also connects to three sniffer receiver (SnRx) inputs that can monitor radio activity in different bands.The high speed JESD204B interface supports lane rates up to 6144 Mbps. Four lanes are dedicated to the transmitters and four lanes are dedicated to the receiver and observation receiver channels.The fully integrated phase-locked loops (PLLs) provide high performance, low power, fractional-N frequency synthesis for the Tx, the Rx, the ORx, and the clock sections. Careful design and layout techniques provide the isolation demanded in high performance base station applications. All voltage controlled oscillator (VCO) and loop filter components are integrated to minimize the external component count.The device contains a fully integrated, low power DPD actuator and adaptation engine for use in PA linearization. The DPD feature enables use of high efficiency PAs, significantly reducing the power consumption of small cell base station radios while also reducing the number of JESD204B lanes necessary to interface with baseband processors.A 1.3 V supply is required to power the AD9375 core, and a standard 4-wire serial port controls it. Other voltage supplies provide proper digital interface levels and optimize transmitter and auxiliary converter performance. The AD9375 is packaged in a 12 mm ? 12 mm, 196-ball chip scale ball grid array (CSP_BGA).Applications 3G/4G small cell base stations (BTS) 3G/4G massive MIMO/active antenna systems

The ADV3202/ADV3203 are 32 ? 16 analog crosspoint switch matrices. They feature a selectable sync-tip clamp input forac-coupled applications and a 2:1 on-screen display (OSD) insertion mux. With ?48 dB of crosstalk and ?80 dB isolationat 5 MHz, the ADV3202/ADV3203 are useful in many high density routing applications. The 0.1 dB flatness out to 60 MHz makes the ADV3202/ADV3203 ideal for both composite and component video switching.The 16 independent output buffers of the ADV3202/ADV3203 can be placed into a high impedance state for paralleling crosspoint outputs so that off-channels present minimal loading to an output bus if building a larger array. The ADV3202 has a gain of +1 while the ADV3203 has a gain of +2 for ease of use in back-terminated load applications. A single +5 V supply, dual ?2.5 V supplies, or dual ?3.3 V supplies can be used while consuming only 195 mA of idle current with all outputs enabled. The channel switching is performed via a double buffered, serial digital control, that can accommodate daisy chaining of several devices.The ADV3202/ADV3203 are packaged in a 176-lead exposed pad LQFP package (24 mm ? 24 mm) and are available over the extended industrial temperature range of ?40?C to +85?C.Applications CCTV surveillance Routing of high speed signals ? ? ? Composite video (NTSC, PAL, S, SECAM) ? ? ? RGB and component video routing ? ? ? Compressed video (MPEG, wavelet) Video conferencingData Sheet, Rev 0, 11/2008

The ADV3224/ADV3225 are high speed 16 ? 8 analog crosspoint switch matrices. They offer a ?3 dB signal bandwidth of greater than 750 MHz and a high slew rate of greater than 2500 V/?s.The ADV3224/ADV3225 include eight independent output buffers that can be placed into a high impedance state for paralleling crosspoint outputs to prevent off channels from loading the output bus. The ADV3224 has a gain of +1 and the ADV3225 has a gain of +2, and they both operate on voltage supplies of ?5 V. Channel switching is performed via a serial digital control that can accommodate the daisy chaining of several devices or via a parallel control to allow updating of an individual output without reprogramming the entire array.The ADV3224/ADV3225 are available in the 72-lead LFCSP package over the extended industrial temperature range of ?40?C to +85?C.Applications Routing of high speed signals including Video (NTSC, PAL, S, SECAM, YUV, RGB) Compressed video (MPEG, wavelet) 3-level digital video (HDB3) Data communications Telecommunications

The ADV3228/ADV3229 are high speed 8 ? 8 analog crosspoint switch matrices. They offer a ?3 dB large signal bandwidth of 750 MHz (ADV3228) and a slew rate of 2500 V/?s.The ADV3228/ADV3229 include eight independent output buffers that can be placed into a high impedance state for paralleling crosspoint outputs to prevent off channels from loading the output bus. The ADV3228 has a gain of +1, the ADV3229 has a gain of +2, and they both operate on voltage supplies of ?5 V. Channel switching is performed via a serial digital control that can accommodate daisy chaining of several devices or via a parallel control to allow updating of an individual output without reprogramming the entire array.The ADV3228/ADV3229 are available in the 72-lead LFCSP package over the extended industrial temperature range of ?40?C to +85?C.Applications Routing of high speed signals including: Video (NTSC, PAL, S, SECAM, YUV, RGB) Compressed video (MPEG, wavelet) 3-level digital video (HDB3) Data communications Telecommunications

The ADA4522-1 / ADA4522-2 / ADA4522-4 are single/dual/quadchannel, zero drift op amps with low noise and power, groundsensing inputs, and rail-to-rail output, optimized for totalaccuracy over time, temperature, and voltage conditions. Thewide operating voltage and temperature ranges, as well as thehigh open-loop gain and very low dc and ac errors make thedevices well suited for amplifying very small input signals andfor accurately reproducing larger signals in a wide variety ofapplications.The ADA4522-1 / ADA4522-2 / ADA4522-4 performance isspecified at 5.0 V, 30 V, and 55 V power supply voltages. Thesedevices operate over the range of 4.5 V to 55 V, and are excellentfor applications using single-ended supplies of 5 V, 10 V, 12 V,and 30 V, or for applications using higher single supplies anddual supplies of ?2.5 V, ?5 V, and ?15 V. The ADA4522-1 / ?ADA4522-2 / ADA4522-4 use on-chip filtering to achieve highimmunity to electromagnetic interference (EMI).The ADA4522-1 / ADA4522-2 / ADA4522-4 are fully specifiedover the extended industrial temperature range of ?40?C to+125?C and are available in 8-lead MSOP, 8-lead SOIC, 14-leadSOIC, and 14-lead TSSOP packages.APPLICATIONS Inductance, capacitance, and resistance (LCR) meter/megohmmeter front-end amplifiers Load cell and bridge transducers Magnetic force balance scales High precision shunt current sensing Thermocouple/resistance temperature detector (RTD) sensors Programmable logic controller (PLC) input and output amplifiers

The ADA4940-1 / ADA4940-2 are low noise, low distortion differential amplifiers with very low power consumption. They are an ideal choice for driving low power, high resolution, high performance SAR and sigma-delta (?-?) analog-to-digital converters (ADCs) with resolutions up to 18 bits from dc to 1 MHz on only 1.25 mA of quiescent current. The adjustable level of the output common-mode voltage allows the ADA4940-1/ ADA4940-2 to match the input common-mode voltage of multiple ADCs. The internal common-mode feedback loop provides exceptional output balance, as well as suppression of even-order harmonic distortion products.With the ADA4940-1 / ADA4940-2, differential gain configurations are easily realized with a simple external feedback network of four resistors determining the closed-loop gain of the amplifier. The ADA4940-1 / ADA4940-2 are fabricated using Analog Devices, Inc., complementary bipolar process, enabling them to achieve very low levels of distortion with an input voltage noise of only 3.9 nV/?Hz. The low dc offset and excellent dynamic performance of the ADA4940-1 / ADA4940-2 make them well suited for a variety of data acquisition and signal processing applications.The ADA4940-1 is available in a Pb-free, 3 mm ? 3 mm, 16-lead LFCSP. The ADA4940-2 is available in a Pb-free, 4 mm ? 4 mm, 24-lead LFCSP. The pinout is optimized to facilitate printed circuit board (PCB) layout and minimize distortion. The ADA4940-1 / ADA4940-2 are specified to operate over the ?40?C to +125?C temperature range.Applications Low power ADC drivers Single-ended-to-differential converters Differential buffers Line drivers Medical Imaging Industrial Process Control Portable Electronics

The LTC1286/LTC1298 are micropower, 12-bit, successive approximation sampling A/D converters. They typically draw only 250?A of supply current when converting and automatically power down to a typical supply current of 1nA whenever they are not performing conversions. They are packaged in 8-pin SO packages and operate on 5V to 9V supplies. These 12-bit, switched-capacitor, successive approximation ADCs include sample-and-holds. The LTC1286 has a single differential analog input. The LTC1298 offers a software selectable 2-channel MUX.On-chip serial ports allow efficient data transfer to a wide range of microprocessors and microcontrollers over three wires. This, coupled with micropower consumption, makes remote location possible and facilitates transmitting data through isolation barriers.These circuits can be used in ratiometric applications or with an external reference. The high impedance analog inputs and the ability to operate with reduced spans (to 1.5V full scale) allow direct connection to sensors and transducers in many applications, eliminating the need for gain stages.Applications Battery-Operated Systems Remote Data Acquisition Battery Monitoring Handheld Terminal Interface Temperature Measurement Isolated Data Acquisition

The LT1372/LT1377 are monolithic high frequency switching regulators. They can be operated in all standard switching configurations including boost, buck, flyback, forward, inverting and 'Cuk.' A 1.5A high efficiency switch is included on the die, along with all oscillator, control and protection circuitry. All functions of the LT1372/LT1377 are integrated into 8-pin SO/PDIP packages.The LT1372/LT1377 typically consumes only 4mA quiescent current and has higher efficiency than previous parts. High frequency switching allows for very small inductors to be used. All surface mount components consume less than 0.5 square inch of board space.New design techniques increase flexibility and maintain ease of use. Switching is easily synchronized to an external logic level source. A logic low on the shutdown pin reduces supply current to 12?A. Unique error amplifier circuitry can regulate positive or negative output voltage while maintaining simple frequency compensation techniques. Nonlinear error amplifier transconductance reduces output overshoot on start-up or overload recovery. Oscillator frequency shifting protects external components during overload conditions.Applications Boost Regulators CCFL Backlight Driver Laptop Computer Supplies Multiple Output Flyback Supplies Inverting Supplies

DC1010A-A: Demo Board for the LTC2493 24-Bit 2-/4-Channel ΔΣ ADC with Easy Drive Input Current Cancellation and I2C Interface.

The LTC2494 is a 16-channel (8-differential), 16-bit, No Latency ??? ADC with Easy Drive technology. The patented sampling scheme eliminates dynamic input current errors and the shortcomings of on-chip buffering through automatic cancellation of differential input current. This allows large external source impedances, and rail-to-rail input signals to be directly digitized while maintaining exceptional DC accuracy. The LTC2494 includes programmable gain, a high accuracy temperature sensor and an integrated oscillator. This device can be configured to measure an external signal (from combinations of 16 analog input channels operating in single-ended or differential modes) or its internal temperature sensor. The integrated temperature sensor offers 1/2?C resolution and 2?C absolute accuracy. The LTC2494 can be configured to provide a programmable gain from 1 to 256 in 8 steps. The LTC2494 allows a wide common mode input range (0V to VCC), independent of the reference voltage. Any combination of single-ended or differential inputs can be selected and the first conversion, after a new channel is selected, is valid.Applications Direct Sensor Digitizer Direct Temperature Measurement Instrumentation Industrial Process Control

Demonstration circuit 1013 is a dual output regulator consisting of two constant-frequency step-down converters, based on the LTC3547 monolithic dual synchronous buck regulator IC. The DC1013 has an input voltage range of 2.5V to 5.5V, and both outputs are capable of delivering up to 300 mA of output current at a minimum input voltage of 3V. In Burst Mode® operation, which is the mode of the LTC3547 during light load current operation, the DC supply current of the DC1013 is typically only 40 uA (per channel) at no load, and less than 1 uA in shutdown. The DC1013 is a very efficient circuit: over 95% for either circuit. The LTC3547 comes in a tiny 8-lead 3 × 2 mm DFN package, which has an exposed pad on the bottom-side of the IC for better thermal performance.

DC1016A-B Demo Board for: LT6557 500MHz, 2200V/µs Gain of 2, Single Supply Triple Video Amplifier with Input Bias Control LT6558 550MHz, 2200V/µs Gain of 1, Single Supply Triple Video Amplifier with Input Bias Control

Demonstration circuit 1025 is a step-down converter, using the LTC3560 monolithic synchronous buck regulator. The DC1025 has an input voltage range of 2.5V to 5.5V, and is capable of delivering up to 800 mA of output current. The output voltage of the DC1025 can be set as low as 0.6V, the reference voltage of the LTC3560. At low load currents, the DC1025 can operate in either noise sensitive applications, due to the capability of the LTC3560 to operate in pulse-skipping mode, or in high efficiency applications, because the LTC3560 can also operate in Burst-Mode.

The LT1336 is a cost effective half-bridge N-channel power MOSFET driver. The floating driver can drive the topside N-channel power MOSFETs operating off a high voltage (HV) rail of up to 60V (absolute maximum). In PWM operation an on-chip switching regulator maintains charge in the bootstrap capacitor even when approaching and operating at 100% duty cycle. The internal logic prevents the inputs from turning on the power MOSFETs in a half-bridge at the same time. Its unique adaptive protection against shoot-through currents eliminates all matching requirements for the two MOSFETs. This greatly eases the design of high efficiency motor control and switching regulator systems. During low supply or start-up conditions, the undervoltage lockout actively pulls the driver outputs low to prevent the power MOSFETs from being partially turned on. The 0.5V hysteresis allows reliable operation even with slowly varying supplies.Applications PWM of High Current Inductive Loads Half-Bridge and Full-Bridge Motor Control Synchronous Step-Down Switching Regulators 3-Phase Brushless Motor Drive High Current Transducer Drivers Class D Power Amplifiers