The AD9680 is a dual, 14-bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed for sampling wide bandwidth analog signals of up to 2 GHz. The AD9680 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.The analog input and clock signals are differential inputs. Each ADC data output is internally connected to two digital down-converters (DDCs). Each DDC consists of up to five cascaded signal processing stages: a 12-bit frequency translator (NCO), and four half-band decimation filters. The DDCs are bypassed by default.In addition to the DDC blocks, the AD9680 has several functions that simplify the automatic gain control (AGC) function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, or four-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF? and SYNCINB? input pins.The AD9680 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V to 3.3 V capable, 3-wire SPI.The AD9680 is available in a Pb-free, 64-lead LFCSP and is specified over the ?40?C to +85?C industrial temperature range. This product is protected by a U.S. patent.PRODUCT HIGHLIGHTS Wide full power bandwidth supports IF sampling of signals up to 2 GHz. Buffered inputs with programmable input termination eases filter design and implementation. Four integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers. Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements. Programmable fast overrange detection. 9 mm ? 9 mm, 64-lead LFCSP.APPLICATIONS Communications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE General-purpose software radios Ultrawideband satellite receivers Instrumentation Radars Signals intelligence (SIGINT) DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers

The AD9680 is a dual, 14-bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed for sampling wide bandwidth analog signals of up to 2 GHz. The AD9680 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.The analog input and clock signals are differential inputs. Each ADC data output is internally connected to two digital down-converters (DDCs). Each DDC consists of up to five cascaded signal processing stages: a 12-bit frequency translator (NCO), and four half-band decimation filters. The DDCs are bypassed by default.In addition to the DDC blocks, the AD9680 has several functions that simplify the automatic gain control (AGC) function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, or four-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF? and SYNCINB? input pins.The AD9680 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V to 3.3 V capable, 3-wire SPI.The AD9680 is available in a Pb-free, 64-lead LFCSP and is specified over the ?40?C to +85?C industrial temperature range. This product is protected by a U.S. patent.PRODUCT HIGHLIGHTS Wide full power bandwidth supports IF sampling of signals up to 2 GHz. Buffered inputs with programmable input termination eases filter design and implementation. Four integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers. Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements. Programmable fast overrange detection. 9 mm ? 9 mm, 64-lead LFCSP.APPLICATIONS Communications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE General-purpose software radios Ultrawideband satellite receivers Instrumentation Radars Signals intelligence (SIGINT) DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers

The AD9689 is a dual, 14-bit, 2.0 GSPS/2.6 GSPS analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of direct sampling wide bandwidth analog signals of up to 5 GHz. The ?3 dB bandwidth of the ADC input is 9 GHz. The AD9689 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The analog input and clock signals are differential inputs. The ADC data outputs are internally connected to four digital downconverters (DDCs) through a crossbar mux. Each DDC consists of multiple cascaded signal processing stages: a 48-bit frequency translator (numerically controlled oscillator (NCO)), and decimation rates. The NCO has the option to select preset bands over the general-purpose input/output (GPIO) pins, which enables the selection of up to three bands. Operation of the AD9689 between the DDC modes is selectable via SPI-programmable profiles.In addition to the DDC blocks, the AD9689 has several functions that simplify the automatic gain control (AGC) function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect control bits in Register 0x0245 of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. In addition to the fast detect outputs, the AD9689 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC.The user can configure the Subclasss 1 JESD204B-based high speed serialized output in a variety of one-lane, two-lane, four-lane, and eight-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multidevice synchronization is supported through the SYSREF? and SYNCINB? input pins.The AD9689 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 3-wire serial port interface (SPI).The AD9689 is available in a Pb-free, 196-ball BGA, specified over the ?40?C to +85?C ambient temperature range. This product is protected by a U.S. patent.Note that throughout this data sheet, multifunction pins, such as FD_A/GPIO_A0, are referred to either by the entire pin name or by a single function of the pin, for example, FD_A, when only that function is relevant.Product Highlights Wide, input ?3 dB bandwidth of 9 GHz supports direct radio frequency (RF) sampling of signals up to about 5 GHz. Four integrated, wideband decimation filters and NCO blocks supporting multiband receivers. Fast NCO switching enabled through the GPIO pins. SPI controls various product features and functions to meet specific system requirements. Programmable fast overrange detection and signal monitoring. On-chip temperature diode for system thermal management. 12 mm ? 12 mm, 196-ball BGA. Pin, package, feature, and memory map compatible with the AD9208 14-bit, 3.0 GSPS, JESD204B dual ADC.Applications Diversity multiband and multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, and GSM, LTE, LTE-A Electronic test and measurement systems Phased array radar and electronic warfare DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers

The AD9704/AD9705/AD9706/AD9707?are the fourth-generation family in the TxDAC series of high performance, CMOS digital-to-analog converters (DACs). This pin-compatible, 8-/10-/12-/14-bit resolution family is optimized for low power operation, while maintaining excellent dynamic performance. The AD9704/AD9705/AD9706/AD9707 family is pin-compatible with the AD9748/AD9740/AD9742/AD9744 family of TxDAC converters and is specifically optimized for the transmit signal path of communication systems. All of the devices share the same interface, LFCSP package, and pinout, providing an upward or downward component selection path based on performance, resolution, and cost. The AD9704/AD9705/AD9706/AD9707 offers exceptional ac and dc performance, while supporting update rates up to 175 MSPS.The flexible power supply operating range of 1.7 V to 3.6 V and low power dissipation of the AD9704/AD9705/AD9706/AD9707 parts make them well suited for portable and low power applications.Power dissipation of the AD9704/AD9705/AD9706/AD9707 can be reduced to 15 mW, with a small trade-off in performance, by lowering the full-scale current output. In addition, a power-down mode reduces the standby power dissipation to approximately 2.2 mW.The AD9704/AD9705/AD9706/AD9707 has an optional serial peripheral interface (SPI?) that provides a higher level of programmability to enhance performance of the DAC. An adjustable output, common-mode feature allows for easy interfacing to other components that require common modes from 0 V to 1.2 V.Edge-triggered input latches and a 1.0 V temperature-compensated band gap reference have been integrated to provide a complete, monolithic DAC solution. The digital inputs support 1.8 V and 3.3 V CMOS logic families.PRODUCT HIGHLIGHTS Pin Compatible. The AD9704/AD9705/AD9706/AD9707 line of TxDAC?converters is pin-compatible with theAD9748/AD9740/AD9742/AD9744 TxDAC line (LFCSP package). Low Power. Complete CMOS DAC operates on a single supply of 3.6 V down to 1.7 V, consuming 50 mW (3.3 V) and 12 mW (1.8 V). The DAC full-scale current can be reduced for lower power operation. Sleep and power-down modes are provided for low power idle periods. Self-Calibration. Self-calibration enables true 14-bit INL and DNL performance in the AD9707. Twos Complement/Binary Data Coding Support. Data input supports twos complement or straight binary data coding. Flexible Clock Input. A selectable high speed, single-ended,and differential CMOS clock input supports 175 MSPS conversion rate. Device Configuration. Device can be configured through pin strapping, and SPI control offers a higher level of programmability. Easy Interfacing to Other Components. Adjustable common-mode output allows for easy interfacing to other signal chain components that accept common-mode levels from 0 V to 1.2 V. On-Chip Voltage Reference. The AD9704/AD9705/AD9706/AD9707 include a 1.0 V temperature-compensated band gap voltage reference. Industry-Standard 32-Lead LFCSP Package.

The AD9737A/AD9739A are 11-bit and 14-bit, 2.5 GSPS high performance RF DACs that are capable of synthesizing wideband signals from dc up to 3 GHz. The AD9737A/AD9739A are pin and functionally compatible with the AD9739 with the exception that the AD9737A/AD9739A do not support synchronization or RZ mode, and are specified to operate between 1.6 GSPS and 2.5 GSPS. By elimination of the synchronization circuitry, some nonideal artifacts such as images and discrete clock spurs remain stationary on the AD9737A/AD9739A between power-up cycles, thus allowing for possible system calibration. AC linearity and noise performance remain the same between the AD9739 and the AD9737A/AD9739A.The inclusion of on-chip controllers simplifies system integration. A dual-port, source synchronous, LVDS interface simplifies the digital interface with existing FGPA/ASIC technology. On-chip controllers are used to manage external and internal clock domain variations over temperature to ensure reliable data transfer from the host to the DAC core. A serial peripheral interface (SPI) is used for device configuration as well as readback of status registers.The AD9737A/AD9739A are manufactured on a 0.18 ?m CMOS process and operate from 1.8 V and 3.3 V supplies. They are supplied in a 160-ball chip scale ball grid array for reduced package parasitics.Product Highlights Ability to synthesize high quality wideband signals with bandwidths of up to 1.25 GHz in the first or second Nyquist zone. A proprietary quad-switch DAC architecture provides exceptional ac linearity performance while enabling mixmode operation. A dual-port, double data rate, LVDS interface supports the maximum conversion rate of 2500 MSPS. On-chip controllers manage external and internal clock domain skews. Programmable differential current output with an 8.66 mA to 31.66 mA range.Applications Broadband communications systems DOCSIS CMTS systems Military jammers Instrumentation, automatic test equipment Radar, avionics

The AD9743/AD9745/AD976/AD9747 are pin-compatible, high dynamic range, dual digital-to-analog converters (DACs) with 10-/12-/14-/16-bit resolutions and sample rates of up to 250 MSPS. The devices include specific features for direct conversion transmit applications, including gain and offset compensation, and they interface seamlessly with analog quadrature modulators, such as the ADL5370.A proprietary, dynamic output architecture permits synthesis of analog outputs even above Nyquist by shifting energy away from the fundamental and into the image frequency.A serial peripheral interface (SPI) port provides full programmability. In addition, some pin-programmable features are offered for those applications without a controller.PRODUCT HIGHLIGHTS Low noise and intermodulation distortion (IMD) enables high quality synthesis of wideband signals. Proprietary switching output for enhanced dynamic performance. Programmable current outputs and dual auxiliary DACs provide flexibility and system enhancements.APPLICATIONS Wireless infrastructure: W-CDMA, CDMA2000, TD-SCDMA, WiMAX Wideband communications: LMDS/MMDS, point-to-point Instrumentation: Radio Frequency (RF) signal generators, arbitrary waveform generators

The ADMV4828 is a silicon on insulator (SOI), 24.0 GHz to 29.5 GHz, mmW 5G beamformer. The RF integrated circuit (RFIC) is highly integrated and contains 16 independent transmit and receive channels. The ADMV4828 supports eight horizontal and eight vertical polarized antennas via independent RFV and RFH input/outputs.In transmit mode, both the RFV input and RFH input signals feed into separate amplifiers. Each path after the amplifiers splits into eight independent channels via the 1:8 power splitters. In receive mode, input signals pass through either the vertical or horizontal receive channels and combine via two independent 8:1 combiners to the common RFV pin or RFH pin. In either mode, each transmit and receive channel includes a vector modulator (VM) to control the phase, and two digital variable gain amplifiers (DVGAs) to control the amplitude. The VM provides a full 360? phase adjustment range in either transmit or receive mode to provide 6 bits of resolution for 5.625? phase steps. A phase step policy for the transmit and receive VM is provided to ensure optimum phase step performance. The total DVGA dynamic range in transmit mode is 34.5, which provides 6 bits of resolution that results in 0.5 dB amplitude steps and 5 bits of resolution that results in 1 dB amplitude steps. In receive mode, the total dynamic range is 28 dB, which provides 5 bits of resolution that results in 0.5 dB amplitude steps and 5 bits of resolution that results in 1 dB amplitude steps. The DVGAs provide a flat phase response across the full gain range. A gain policy for DVGA1 and DVGA2 is provided in the AN-2074 Application Note, ADMV4828 Application Note to ensure optimized performance across the attenuation range with 0.5 dB step resolution from 0 dB to 34.5 dB attenuation for transmit mode and 0.5 dB step resolution from 0 dB to 28 dB attenuation for receive mode. The transmit channels contain individual transmit power detectors to detect either modulated or continuous wave signals to calibrate for each channel gain as well as channel to channel gain mismatch. Each receive channel contains an RF power overload circuit (receive channel overload detection circuit) to prevent potential damage to the device as a result of blocker instances. The ADMV4828 RF ports can be connected directly to a patch antenna to create a dual polarization mmW 5G subarray.The ADMV4828 can be programmed using a 3-wire or 4-wire serial port interface (SPI). An integrated, on-chip low dropout (LDO) voltage regulator generates the 1.0 V supply for the SPI circuitry to reduce the number of supply domains required. Various SPI modes are available to enable fast startup and control during normal operation. The amplitude and phase for each channel can be set individually or multiple channels can be programmed simultaneously using the on-chip memory for beamforming. The on-chip memory can store up to 2048 beam positions that can be allocated for either transmit mode or receive mode for the horizontal channels and vertical channels. On-chip nonvolatile memory (NVM) is used to store the calibrated gain and phase offset coefficients and the reference values for each individual channel from the factory. These values are used to perform channel to channel or chip to chip calibration. In addition, four address pins (CHIP_ADDx) allow independent SPI control of up to 16 devices on the same serial lines. To control multiple devices via the same serial lines with the same instructions, activate broadcast mode via the external enable pin (BR_EN). Dedicated horizontal and vertical polarization load pins (LOAD_V and LOAD_H) provide the synchronization of all devices in the same array. A horizontal and vertical polarization transmit mode and receive mode control pin (TRX_H or TRX_V) is provided for fast switching between transmit mode and receive mode.The ADMV4828 comes in a compact, 304-ball, 10 mm ? 8.5 mm chip scale package ball grid array (CSP_BGA). The ADMV4828 operates over the ?40?C to +95?C case temperature (TC) range. This CSP_BGA package enables the ability to heatsink the ADMV4828 from the topside of the package for the most efficient thermal heatsinking and to allow flexible antenna placement on the opposite side of the printed circuit board (PCB).APPLICATIONSmmW 5G applicationBroadband communication

The ADMV7320 is a fully integrated system in package (SiP),in phase/quadrature (I/Q) upconverter that operates betweenan intermediate frequency (IF) input range of dc and 2 GHzand a radio frequency (RF) output range of 81 GHz and 86 GHz.The device uses an image rejection mixer that is driven by a 6?local oscillator (LO) multiplier. The mixer RF output is followedby a variable gain amplifier (VGA) and a power amplifier (PA),providing a conversion gain of 33 dB typical. Differential I andQ mixer inputs are provided and can be driven with differentialI and Q baseband waveforms for direct conversion applications.Alternatively, the inputs can be driven using an external 90? hybridand two external 180 hybrids for single-ended applications.The ADMV7320 comes in a fully integrated, surface-mount,50-terminal, 16.00 mm ? 14.00 mm, chip array small outline nolead cavity (LGA_CAV) package. The ADMV7320 operatesover the ?40?C to +85?C temperature range.APPLICATIONS E-band communication systems High capacity wireless backhauls Test and measurement Aerospace and defense

The ADN2830 provides closed loop control of the average optical power of a continuous wave (CW) laser diode (LD) after initial factory setup. The control loop adjusts the laser IBIAS to maintain a constant Back Facet Monitor Photo Diode (MPD) current and hence a constant laser optical power. The external PSET resistor is adjusted during factory set up to set the desired optical power. RPSET is set at 1.23/IAV, where IAVis the MPD current corresponding to the desired optical power. Programmable alarms are provided for laser fail (end of life) and laser degrade (impending fail).The ADN2830 operates from a single power +5 V supply. It is available in 5mm ? 5mm LFCSP-32 Lead Frame Chip Scale.

The ADN88311 is a monolithic TEC controller. It has two integrated, zero drift, rail-to-rail comparators, and a PWM driver. A unique PWM driver works with an analog driver to control external selected MOSFETs in an H-bridge. By sensing the thermal detector feedback from the TEC, the ADN8831 can drive a TEC to settle the programmable temperature of a laser diode or a passive component attached to the TEC module.The ADN8831 supports NTC thermistors or positive temperature coefficient (PTC) RTDs. The target temperature is set as an analog voltage input either from a DAC or from an external resistor divider driven by a reference voltage source.A proportional integral differential (PID) compensation network helps to quickly and accurately stabilize the ADN8831 thermal control loop. An adjustable PID compensation network example is described in the AN-695 Application Note, Using the ADN8831TEC Controller Evaluation Board. A typical reference voltage of 2.5 V is available from the ADN8831 for thermistor temperature sensing or for TEC voltage/current measuring and limiting in both cooling and heating modes.Applications Thermoelectric cooler (TEC) temperature control DWDM optical transceiver modules Optical fiber amplifiers Optical networking systems Instruments requiring TEC temperature control1 Product is covered by U.S. Patent No. 6,486,643

The ADN8833 is a monolithic H-bridge TEC driver with integrat-ed 1 A power MOSFETs. It has a linear power stage with the linear driver (LDR) output and a pulse-width modulation (PWM) power stage with the SW output. Depending on the control voltage at the CONT input, the ADN8833 drives current through a TEC to settle the temperature of a laser diode or a passive component attached to the TEC module to the programmed target temperature.The control voltage applied to the CONT input is generated by a digital-to-analog converter (DAC) closing the digital proportional, integral, derivative (PID) loop of temperature control system.The internal 2.5 V reference voltage provides a 1% accurate output that is used to bias a voltage divider network to program the maximum TEC current and voltage limits for both the heating and cooling modes. It can also be a reference voltage for the DAC and the temperature sensing circuit, including a thermistor bridge and an analog-to-digital converter (ADC).APPLICATIONS TEC temperature control Optical modules Optical fiber amplifiers Optical networking systems Instruments requiring TEC temperature control

The ADN88341 is a monolithic TEC controller with an integrated TEC controller. It has a linear power stage, a pulse-width modulation (PWM) power stage, and two zero-drift, rail-to-rail operational amplifiers. The linear controller works with the PWM driver to control the internal power MOSFETs in an H-bridge configuration. By measuring the thermal sensor feedback voltage and using the integrated operational amplifiers as a proportional integral differential (PID) compensator to condition the signal, the ADN8834 drives current through a TEC to settle the temperature of a laser diode or a passive component attached to the TEC module to the programmed target temperature.The ADN8834 supports negative temperature coefficient (NTC) thermistors as well as positive temperature coefficient (PTC) resistive temperature detectors (RTD). The target temperature is set as an analog voltage input either from a digital-to-analog converter (DAC) or from an external resistor divider.The temperature control loop of the ADN8834 is stabilized by PID compensation utilizing the built in, zero drift chopper amplifiers. The internal 2.50 V reference voltage provides a 1% accurate output that is used to bias a thermistor temperature sensing bridge as well as a voltage divider network to program the maximum TEC current and voltage limits for both the heating and cooling modes. With the zero drift chopper amplifiers, extremely good long-term temperature stability is maintained via an autonomous analog temperature control loop.APPLICATIONS TEC temperature control Optical modules Optical fiber amplifiers Optical networking systems Instruments requiring TEC temperature control1 Product is covered by U.S. Patent No. 6,486,643.

The ADN88341 is a monolithic TEC controller with an integrated TEC controller. It has a linear power stage, a pulse-width modulation (PWM) power stage, and two zero-drift, rail-to-rail operational amplifiers. The linear controller works with the PWM driver to control the internal power MOSFETs in an H-bridge configuration. By measuring the thermal sensor feedback voltage and using the integrated operational amplifiers as a proportional integral differential (PID) compensator to condition the signal, the ADN8834 drives current through a TEC to settle the temperature of a laser diode or a passive component attached to the TEC module to the programmed target temperature.The ADN8834 supports negative temperature coefficient (NTC) thermistors as well as positive temperature coefficient (PTC) resistive temperature detectors (RTD). The target temperature is set as an analog voltage input either from a digital-to-analog converter (DAC) or from an external resistor divider.The temperature control loop of the ADN8834 is stabilized by PID compensation utilizing the built in, zero drift chopper amplifiers. The internal 2.50 V reference voltage provides a 1% accurate output that is used to bias a thermistor temperature sensing bridge as well as a voltage divider network to program the maximum TEC current and voltage limits for both the heating and cooling modes. With the zero drift chopper amplifiers, extremely good long-term temperature stability is maintained via an autonomous analog temperature control loop.APPLICATIONS TEC temperature control Optical modules Optical fiber amplifiers Optical networking systems Instruments requiring TEC temperature control1 Product is covered by U.S. Patent No. 6,486,643.

The ADP1032 is a high performance, isolated micropower management unit (PMU) that combines an isolated flyback and a dc-to-dc regulator providing two isolated power rails. Additionally, the ADP1032 contains four high speed serial peripheral interface (SPI) isolation channels and three general-purpose isolators for channel to channel applications where low power dissipation and small solution size is required. Operating over an input voltage range of 4.5 V to 60 V, the ADP1032 generates isolated output voltages of 6 V to 28 V (adjustable version) or 24 V (fixed version) for VOUT1, and factory programmable voltages of 5.15 V, 5.0 V, or 3.3 V for VOUT2.?By default, the ADP1032 flyback regulator operates at a 250 kHz switching frequency, and the buck regulator operates at 125 kHz.?The two regulators are phase shifted relative to each other to reduce electromagnetic interference (EMI). The ADP1032 can be driven by an external oscillator in the range of 350 kHz to 750 kHz to ease noise filtering in sensitive applications.?The digital isolators integrated in the ADP1032 use Analog Devices, Inc., iCoupler? chip scale transformer technology, optimized for low power and low radiated emissions. The ADP1032 is available in a 9 mm ? 7 mm, 41-lead LFCSP and is rated for a ?40?C to +125?C operating junction temperature range.?

The ADP1032 is a high performance, isolated micropower management unit (PMU) that combines an isolated flyback and a dc-to-dc regulator providing two isolated power rails. Additionally, the ADP1032 contains four high speed serial peripheral interface (SPI) isolation channels and three general-purpose isolators for channel to channel applications where low power dissipation and small solution size is required. Operating over an input voltage range of 4.5 V to 60 V, the ADP1032 generates isolated output voltages of 6 V to 28 V (adjustable version) or 24 V (fixed version) for VOUT1, and factory programmable voltages of 5.15 V, 5.0 V, or 3.3 V for VOUT2.?By default, the ADP1032 flyback regulator operates at a 250 kHz switching frequency, and the buck regulator operates at 125 kHz.?The two regulators are phase shifted relative to each other to reduce electromagnetic interference (EMI). The ADP1032 can be driven by an external oscillator in the range of 350 kHz to 750 kHz to ease noise filtering in sensitive applications.?The digital isolators integrated in the ADP1032 use Analog Devices, Inc., iCoupler? chip scale transformer technology, optimized for low power and low radiated emissions. The ADP1032 is available in a 9 mm ? 7 mm, 41-lead LFCSP and is rated for a ?40?C to +125?C operating junction temperature range.?

The ADP1046A is a flexible, digital secondary side controller designed for ac-to-dc and isolated dc-to-dc secondary sideapplications. The ADP1046A is pin-compatible with theADP1043A and offers several enhancements and new features,including voltage feedforward and improved loop response to maximize efficiency.The ADP1046A is optimized for minimal component count,maximum flexibility, and minimum design time. Featuresinclude local and remote voltage sense, primary and secondary side current sense, digital pulse-width modulation (PWM)generation, current sharing, and redundant OrFET control. The control loop digital filter and compensation terms are integrated and can be programmed over the I2C interface. Programmableprotection features include overcurrent protection (OCP), over-voltage protection (OVP), undervoltage lockout (UVLO), and overtemperature protection (OTP).The built-in EEPROM provides extensive programming of theintegrated loop filter, PWM signal timing, inrush current, andsoft start timing and sequencing. Reliability is improved through a built-in checksum and programmable protection circuits.A comprehensive GUI is provided for easy design of loop filter characteristics and programming of the safety features.The industry-standard I2C bus provides access to the many monitoring and system test functions.The ADP1046A is available in a 32-lead LFCSP and operatesfrom a single 3.3 V supply.APPLICATIONS AC-to-DC power supplies Isolated dc-to-dc power supplies Redundant power supply systems Server, storage, network, and communications infrastructure

The ADP1046A is a flexible, digital secondary side controller designed for ac-to-dc and isolated dc-to-dc secondary sideapplications. The ADP1046A is pin-compatible with theADP1043A and offers several enhancements and new features,including voltage feedforward and improved loop response to maximize efficiency.The ADP1046A is optimized for minimal component count,maximum flexibility, and minimum design time. Featuresinclude local and remote voltage sense, primary and secondary side current sense, digital pulse-width modulation (PWM)generation, current sharing, and redundant OrFET control. The control loop digital filter and compensation terms are integrated and can be programmed over the I2C interface. Programmableprotection features include overcurrent protection (OCP), over-voltage protection (OVP), undervoltage lockout (UVLO), and overtemperature protection (OTP).The built-in EEPROM provides extensive programming of theintegrated loop filter, PWM signal timing, inrush current, andsoft start timing and sequencing. Reliability is improved through a built-in checksum and programmable protection circuits.A comprehensive GUI is provided for easy design of loop filter characteristics and programming of the safety features.The industry-standard I2C bus provides access to the many monitoring and system test functions.The ADP1046A is available in a 32-lead LFCSP and operatesfrom a single 3.3 V supply.APPLICATIONS AC-to-DC power supplies Isolated dc-to-dc power supplies Redundant power supply systems Server, storage, network, and communications infrastructure

The ADP1055 is a flexible, feature-rich digital secondary side controller that targets ac-to-dc and isolated dc-to-dc secondary side applications. The ADP1055 is optimized for minimal component count, maximum flexibility, and minimum design time. Features include differential remote voltage sense, primary and secondary side current sense, pulse-width modulation (PWM) generation, frequency synchronization, redundant OVP, and current sharing. The control loop digital filter and compensation terms are integrated and can be programmed over the PMBus? interface. Programmable protection features include overcurrent (OCP), overvoltage (OVP) limiting, undervoltage lockout (UVLO), and external overtemperature (OTP).The built-in EEPROM provides extensive programming of the integrated loop filter, PWM signal timing, inrush current, and soft start timing and sequencing. Reliability is improved through a built-in checksum and programmable protection circuits.A comprehensive GUI is provided for easy design of loop filter characteristics and programming of the safety features. The industry-standard PMBus provides access to the many monitoring and system test functions. The ADP1055 is available in a 32-lead LFCSP and operates from a single 3.3 V supply.APPLICATIONS Isolated dc-to-dc power supplies and modules Redundant power supply systems

The ADP121 is a quiescent current, low dropout, linear regulator that operates from 2.3 V to 5.5 V and provides up to 150 mA of output current. The low 135 mV dropout voltage at 150 mA load improves efficiency and allows operation over a wide input voltage range. The low 30 ?A of quiescent current at full load makes the ADP121 ideal for battery-operated portable equipment.The ADP121 is available in output voltages ranging from 1.2 V to 3.3 V. The parts are optimized for stable operation with small 1 ?F ceramic output capacitors. The ADP121 delivers good transient performance with minimal board area.Short-circuit protection and thermal overload protection circuits prevent damage in adverse conditions. The ADP121 is available in a tiny 5-lead TSOT and 4-ball 0.4 mm pitch WLCSP pack-ages and utilizes the smallest footprint solution to meet a variety of portable applications.

The ADP121 is a quiescent current, low dropout, linear regulator that operates from 2.3 V to 5.5 V and provides up to 150 mA of output current. The low 135 mV dropout voltage at 150 mA load improves efficiency and allows operation over a wide input voltage range. The low 30 ?A of quiescent current at full load makes the ADP121 ideal for battery-operated portable equipment.The ADP121 is available in output voltages ranging from 1.2 V to 3.3 V. The parts are optimized for stable operation with small 1 ?F ceramic output capacitors. The ADP121 delivers good transient performance with minimal board area.Short-circuit protection and thermal overload protection circuits prevent damage in adverse conditions. The ADP121 is available in a tiny 5-lead TSOT and 4-ball 0.4 mm pitch WLCSP pack-ages and utilizes the smallest footprint solution to meet a variety of portable applications.