The ADA4961 is a high performance, BiCMOS RF digital gain?amplifier (DGA), optimized for driving heavy loads out to 2.0 GHz and beyond. The device typically achieves ?90 dBc?IMD3 performance at 500 MHz and ?85 dBc at 1.5 GHz. This?RF performance allows GHz converters to achieve their optimum?performance with minimal limitations of the driver amplifier or constraints on overall power that typically result from GaAs amplifiers. This device can easily drive 10-bit to 16-bit HS?converters.For many receiver applications, antialias filter (AAF) designs?can be simplified or not required.The ADA4961 has an internal differential input impedance of 100 ? and a differential dynamic output impedance of 50 ?,?eliminating the need for external termination resistors. The?digital adjustability provides for 1 dB resolution, thus optimizing the signal-to-noise ratio (SNR) for input levels spanning 21 dB.The ADA4961 is optimized for wideband, low distortion?performance at frequencies up to 2 GHz. These attributes,?together with wide gain adjustment and relatively low power, make the ADA4961 the amplifier of choice for many high speed?applications, including IF, RF, and broadband applications where dynamic range at very high frequencies is critical.The ADA4961 is ideally suited for driving not only analog-to-digital converters (ADCs), but also mixers, pin diode attenuators,?SAW filters, and multielement discrete devices. It is available in a 4 mm ? 4 mm, 24-lead LFCSP and operates over a?temperature range of ?40?C to +85?C. Applications ADC driver for 10-bit to 14-bit GSPS converters RF/IF gain blocks Line drivers Instrumentation Satellite communications Data acquisition Military systems

The ADF4108 frequency synthesizer can be used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. It consists of a low-noise digital PFD (phase frequency detector), a precision charge pump, a programmable reference divider, programmable A and B counters, and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B (13-bit) counters, in conjunction with the dual-modulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R counter), allows selectable REFIN frequencies at the PFD input. A complete PLL (phase-locked loop) can be implemented if the synthesizer is used with an external loop filter and VCO (voltage controlled oscillator). Its very high bandwidth (8GHz) means that frequency doublers or prescalers can be eliminated in many high frequency systems, simplifying system architecture and reducing cost.Applications Broadband wireless access Satellite systems Instrumentation Wireless LANs Base stations for wireless radio

The ADF4193 frequency synthesizer can be used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. Its architecture is specifically designed to meet the GSM/EDGE lock time requirements for base stations. It consists of a low noise, digital phase frequency detector (PFD), and a precision differential charge pump. There is also a differential amplifier to convert the differential charge pump output to a single-ended voltage for the external voltage-controlled oscillator (VCO).The ?-?-based fractional interpolator, working with the N divider, allows programmable modulus fractional-N division. Additionally, the 4-bit reference (R) counter and on-chip frequency doubler allow selectable reference signal (REFIN) frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and a VCO. The switching architecture ensures that the PLL settles inside the GSM time slot guard period, removing the need for a second PLL and associated isolation switches. This decreases cost, complexity, PCB area, shielding, and characterization on previous ping-pong GSM PLL architectures.Applications GSM/EDGE base stations PHS base stations Instrumentation and test equipment

The ADF4360-7?is an integrated integer-N synthesizer and voltage controlled oscillator (VCO). The ADF4360-7 center frequency is set by external inductors. This allows a frequency range of between 350 MHz to 1800 MHz. In addition, a divide-by-2 option is available, whereby the user receives an RF output of between 175 MHz and 900 MHz.Control of all the on-chip registers is through a simple 3-wire interface. The device operates with a power supply ranging from 3.0 V to 3.6 V and can be powered down when not in use.APPLICATIONS Wireless handsets (DECT, GSM, PCS, DCS, WCDMA) Test equipment Wireless LANs CATV equipment

The ADF4372 allows implementation of fractional-N or integer-N phase-locked loop (PLL) frequency synthesizers when used with an external loop filter and an external reference frequency. The wideband microwave voltage controlled oscillator (VCO) design allows frequencies from 62.5 MHz to 16 GHz to be generated.The ADF4372 has an integrated VCO with a fundamental output frequency ranging from 4000 MHz to 8000 MHz. In addition, the VCO frequency is connected to a divide by 1, 2, 4, 8, 16, 32, or 64 circuit that allows the user to generate radio frequency (RF) output frequencies as low as 62.5 MHz at RF8x. A frequency multiplier at RF16x generates from 8 GHz to 16 GHz. RFAUX8x duplicates the frequency range of RF8x or permits direct access to the VCO output. To suppress the unwanted products of frequency multiplication, a harmonic filter exists between the multiplier and the output stage of RF16x.Control of all on-chip registers is through a 3-wire interface. The ADF4372 operates with analog and digital power supplies ranging from 3.15 V to 3.45 V, and 5 V for the VCO power supply. The ADF4372 also contains hardware and software power-down modes.APPLICATIONS Wireless infrastructure (multicarrier global system for mobile communication (MC-GSM), 5 G) Test equipment and instrumentation Clock generation Aerospace and defense

The ADF5355 allows implementation of fractional-N or integer-N phase-locked loop (PLL) frequency synthesizers when used with an external loop filter and an external reference frequency. The wideband microwave VCO design permits frequency operation from 6.8 GHz to 13.6 GHz at one radio frequency (RF) output. A series of frequency dividers at another frequency output permits operation from 54 MHz to 6800 MHz.The ADF5355 has an integrated VCO with a fundamental output frequency ranging from 3400 MHz to 6800 MHz. In addition, the VCO frequency is connected to divide by 1, 2, 4, 8, 16, 32, or 64 circuits that allow the user to generate RF output frequencies as low as 54 MHz. For applications that require isolation, the RF output stage can be muted. The mute function is both pin and software controllable.Control of all on-chip registers is through a simple 3-wire interface. The ADF5355 operates with analog and digital power supplies ranging from 3.15 V to 3.45 V, with charge pump and VCO supplies from 4.75 V to 5.25 V. The ADF5355 also contains hardware and software power-down modes.Applications Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX, GSM, PCS, DCS, DECT) Point to point/point to multipoint microwave links Satellites/VSATs Test equipment/instrumentation Clock generation

The ADF5709 wideband, monolithic microwave integrated circuit (MMIC), voltage controlled oscillator (VCO) supports an output frequency (fOUT) range of 9.85 GHz to 20.5 GHz while maintaining ?83 dBc/Hz phase noise at 100 kHz offset without subharmonic tones. The wide frequency tuning range and low phase noise allow phase-locked loop (PLL) solutions for a variety of frequency bands and limit the need for multiple narrow-band VCOs. The broad frequency coverage reduces the board design complexity and simplifies the bill of materials when designing RF and microwave applications.The VCO operates from a single 5 V supply and consumes only 70 mA of supply current that results in minimal power dissipation. The ADF5709 low power consumption is ideal for high performance applications with limited or no airflow. The monolithic construction of the VCO allows optimal output power and noise characteristics over temperature variations.The VCO is fully integrated and incorporates a resonator, a negative resistance device, and a varactor diode that minimize the number of external components and reduces board space.The low input impedance on the VTUNE pin of the ADF5709 enables high tuning speed and modulation bandwidth, which allows faster frequency sweeps and lock times when used as part of a frequency synthesizer, for example, in radar or in test and measurement applications.The ADF5709 is encapsulated into a tiny, 3.90 mm ? 3.90 mm, RoHS compliant, ceramic leadless chip carrier (LCC) package. The package includes through vias to the exposed pad, enhancing thermal characteristics.The small size, optimal noise performance, low power consumption, and wide tuning range of the ADF5709 make the device ideal for many applications requiring flexibility, high performance, a small footprint, and a tight power budget. The ADF5709 is pin to pin compatible with the HMC733 and other Analog Devices, Inc., wideband VCOs.APPLICATIONSIndustrial and medical equipmentTest and measurement equipmentMilitary radars, electronic warfare (EW), and electronic countermeasures (ECMs)Point to point and multipoint radiosVery small aperture terminals (VSATs)Wireless communication infrastructure

The ADF5904 is a 4-channel, 24 GHz, receiver downconverter.Each channel contains a single-ended RF input with an on-chipbalun followed by a differential low noise amplifier (LNA) and adownconverter mixer with differential output buffers. The RFLO path also has an on-chip balun.Control of the on-chip registers is through a simple 3-wireinterface.The ADF5904 comes in a compact 32-lead, 5 mm ? 5 mmLFCSP package.Applications Automotive radars Industrial radars Microwave (?W) radar sensors

The ADF7030-1 is a fully integrated, radio transceiver achieving high performance at very low power. The ADF7030-1 is ideally suited for applications that require long range, network robustness, and long battery life. It is suitable for applications that operate in the ISM, SRD, and licensed frequency bands at 169.4 MHz to 169.6 MHz, 426 MHz to 470 MHz, and 863 MHz to 960 MHz. It provides extensive support for standards-based protocols like IEEE802.15.4g while also providing flexibility to support a wide range of proprietary protocols.The highly configurable low intermediate frequency (IF) receiver supports a large range of receiver channel bandwidths from 2.6 kHz to 406 kHz. This range of receiver channel bandwidths allows the ADF7030-1 to support ultranarrow-band, narrow-band, and wideband channel spacing.The ADF7030-1 features two independent PAs supporting output power ranges of ?20 dBm to +13 dBm and ?20 dBm to +17 dBm. The PAs support ultrafine adjustment of the power with a step resolution of 0.1 dB. The PA output power is exceptionally robust over temperature and voltage. The PAs have an automatic power ramp control to limit spectral splatter to meet regulatory standards.The ADF7030-1 features an on-chip ARM??Cortex?-M0 processor that performs radio control, radio calibration, and packet management. Cortex-M0 eases the processing burden of the host processor because the ADF7030-1 integrates the lower layers of a typical communication protocol stack. This internal processor also permits the download and execution of Analog Devices, Inc., provided firmware modules that can extend the functionality of the ADF7030-1.The ADF7030-1 has two packet modes: generic packet mode and IEEE802.15.4g mode. In generic packet mode, the packet format is highly flexible and fully programmable, thereby ensuring its compatibility with proprietary packet formats. In IEEE802.15.4g packet mode, the packet format conforms to the?IEEE802.15.4g standard. FEC, as per the IEEE802.15.4g standard, is also supported.The ADF7030-1 operates with a power supply range of 2.2 V to 3.6 V and has very low power consumption in both Tx and Rx modes, enabling long lifetimes in battery-operated systems. An ultralow power deep sleep mode achieves a typical current of 10 nA with the configuration memory retained.A complete wireless solution can be built using a small number of external discrete components and a host processor (typically a microcontroller). The host processor can configure the ADF7030-1 using a simple command-based protocol over a standard 4-wire SPI interface. A single-byte command transitions the radio between states or performs a radio function.The ADF7030-1 is available in two package types: a 6 mm ? 6 mm, 40-lead LFCSP and a 7 mm ? 7 mm, 48-lead LQFP. Both package types use NiPdAu plating to mitigate against silver migration in high humidity applications. The ADF7030-1 operating temperature range is ?40?C to +85?C.For Figure 13 to Figure 19, Figure 30, Figure 42, Figure 60, Figure 61, and Figure 75 in the Typical Performance Characteristics section, PA_COARSE is a programmable value that provides a coarse adjustment of the PA output power. This value can be programmed in the range of 1 to 6 for PA1, and from 1 to 10 for PA2. PA_FINE is a programmable value that provides a fine adjustment of the PA output power. This value can be programmed in the range of 3 to 127 for both PA1 and PA2. PA_MICRO is a programmable value that provides a microadjustment (typically

The ADF7030-1 is a fully integrated, radio transceiver achieving high performance at very low power. The ADF7030-1 is ideally suited for applications that require long range, network robustness, and long battery life. It is suitable for applications that operate in the ISM, SRD, and licensed frequency bands at 169.4 MHz to 169.6 MHz, 426 MHz to 470 MHz, and 863 MHz to 960 MHz. It provides extensive support for standards-based protocols like IEEE802.15.4g while also providing flexibility to support a wide range of proprietary protocols.The highly configurable low intermediate frequency (IF) receiver supports a large range of receiver channel bandwidths from 2.6 kHz to 406 kHz. This range of receiver channel bandwidths allows the ADF7030-1 to support ultranarrow-band, narrow-band, and wideband channel spacing.The ADF7030-1 features two independent PAs supporting output power ranges of ?20 dBm to +13 dBm and ?20 dBm to +17 dBm. The PAs support ultrafine adjustment of the power with a step resolution of 0.1 dB. The PA output power is exceptionally robust over temperature and voltage. The PAs have an automatic power ramp control to limit spectral splatter to meet regulatory standards.The ADF7030-1 features an on-chip ARM??Cortex?-M0 processor that performs radio control, radio calibration, and packet management. Cortex-M0 eases the processing burden of the host processor because the ADF7030-1 integrates the lower layers of a typical communication protocol stack. This internal processor also permits the download and execution of Analog Devices, Inc., provided firmware modules that can extend the functionality of the ADF7030-1.The ADF7030-1 has two packet modes: generic packet mode and IEEE802.15.4g mode. In generic packet mode, the packet format is highly flexible and fully programmable, thereby ensuring its compatibility with proprietary packet formats. In IEEE802.15.4g packet mode, the packet format conforms to the?IEEE802.15.4g standard. FEC, as per the IEEE802.15.4g standard, is also supported.The ADF7030-1 operates with a power supply range of 2.2 V to 3.6 V and has very low power consumption in both Tx and Rx modes, enabling long lifetimes in battery-operated systems. An ultralow power deep sleep mode achieves a typical current of 10 nA with the configuration memory retained.A complete wireless solution can be built using a small number of external discrete components and a host processor (typically a microcontroller). The host processor can configure the ADF7030-1 using a simple command-based protocol over a standard 4-wire SPI interface. A single-byte command transitions the radio between states or performs a radio function.The ADF7030-1 is available in two package types: a 6 mm ? 6 mm, 40-lead LFCSP and a 7 mm ? 7 mm, 48-lead LQFP. Both package types use NiPdAu plating to mitigate against silver migration in high humidity applications. The ADF7030-1 operating temperature range is ?40?C to +85?C.For Figure 13 to Figure 19, Figure 30, Figure 42, Figure 60, Figure 61, and Figure 75 in the Typical Performance Characteristics section, PA_COARSE is a programmable value that provides a coarse adjustment of the PA output power. This value can be programmed in the range of 1 to 6 for PA1, and from 1 to 10 for PA2. PA_FINE is a programmable value that provides a fine adjustment of the PA output power. This value can be programmed in the range of 3 to 127 for both PA1 and PA2. PA_MICRO is a programmable value that provides a microadjustment (typically

The HMC1035LP6GE is a low-noise, wide-band 3.3 V clock generator IC with a fractional-N Phase Locked Loop (PLL) that features an integrated Voltage Controlled Oscillator (VCO). The device provides differential clock outputs between 25 MHz and 2500 MHz range. The HMC1035LP6GE features a low noise Phase Detector (PD) and Delta-Sigma modulator, capable of operating at up to 100 MHz which permits wider loop-bandwidths and excellent spurious performance.The HMC1035LP6GE features industry leading phase noise and jitter performance, across the operating range, that enable it to improve link level jitter performance, Bit-Error-Rates (BER) and eye diagram metrics. The superior noise floor (

The HMC1197 is a low noise, high linearity Direct Quadrature Modulator with Fractional-N PLL&VCO RFIC which is ideal for digital modulation applications from 0.1 to 4.0 GHz including; Cellular/3G, LTE/WiMAX/4G, Broadband Wireless Access & ISM circuits housed in a compact 7x7 mm (LP7) SMT QFN package, the HMC1197 RFIC requires minimal external components & provides a low cost alternative to more complicated double upconversion architectures. The RF output port is single-ended and matched to 50 Ohms with no external components.Auxiliary LO output (differential or single-ended), enables the HMC1197 to distribute identical frequency and phase signals to multiple destinations. Individual gain settings ensure optimal signal levels tailored to each output.External VCO input allows the HMC1197 to lock external VCOs, and enables cascaded LO architectures for MIMO radio applications. Two separate Charge Pump (CP) outputs enable separate loop filters optimized for both integrated and external VCOs, and seamless switching between integrated or external VCOs during operation. Programmable RF output phase feature can further phase adjust and synchronize multiple HMC1197s enabling scalable MIMO and beam-forming radio architectures.Integrated programmable Low Pass Filter (LPF) on the modulator LO input ensures no LO harmonic contribution to modulator sideband rejection performance. Sixteen programmable LPF bands enable true wideband operation, eliminating the need for external band specific harmonic filtering hardware.Additional features include configurable LO output mute function. Exact Frequency Mode that enables the HMC1197 to generate fractional frequencies with 0 Hz frequency error and the ability to synchronously change frequencies without changing the phase of the output signal. APPLICATIONS Multiband/Multi-standard Cellular BTS Diversity Transmitters Fixed Wireless or WLL ISM Transceivers, 900 & 2400 MHz GMSK, QPSK, QAM, SSB Modulators Multiband Basestations & Repeaters

The HMC661LC4B is a SiGe monolithic, fully differential, single rank, track-and-hold (T/H) that provides unprecedented bandwidth and dynamic-range performance to wideband sampled signal systems. The T/H offers precision signal sampling over 18 GHz bandwidth, with 9-10-bit linearity from DC to beyond 5 GHz input frequency, 1.05 mV noise, and

The HMC747 is a D-Type Flip-Flop designed to support data transmission rates of up to 13 Gbps, and clock frequencies as high as 13 GHz. During normal operation, data is transferred to the outputs on the positive edge of the clock. Reversing the clock inputs allows for negative-edge triggered applications. The HMC747 also features an output level control pin, VR, which allows for loss compensation or for signal level optimization.All input and output signals to the HMC747 are terminated with 50 ? to VCC on-chip, and may be either AC or DC coupled. Inputs and outputs can be connected directly to a 50 ??to VCC terminated system, while DC blocking capacitors may be used if the terminating system is 50 ??to ground. The HMC747 operates from a single +3.3V DC supply and is available in a ceramic RoHS compliant 3?3 mm SMT package.APPLICATIONS RF ATE Applications Broadband Test & Measurement Serial Data Transmission up to 13 Gbps Digital Logic Systems up to 13 GHz

The HMC829LP6GE is a low noise, wide band, Fractional-N Phase-Locked-Loop (PLL) that features an integrated Voltage Controlled Oscillator (VCO ) with a fundamental frequency of 2800 MHz - 4200 MHz, and an integrated VCO Output Divider (divide by 1/2/4/6.../60/62), that together allow the HMC829LP6GE to generate frequencies from 45 MHz to 1050 MHz, from 1400 MHz to 2100 MHz, and from 2800 MHz to 4200 MHz. The integrated Phase Detector (PD) and delta-sigma modulator, capable of operating at up to 100 MHz, permit wider loop-bandwidths with excellent spectral performance.For theory of operation and register map refer to the 'PLLs w/ Integrated VCO - Microwave VCOs' Operating Guide.Applications Cellular/4G, WiMax Infrastructure Repeaters and Femtocells Communications Test Equipment CATV Equipment Phased Array Applications DDS Replacement Very High Data Rate Radios

The HMC865LC3 is a Limiting Amplifier packaged in a leadless 3x3 mm ceramic surface mount package which supports up to 43 Gbps operation. The amplifier provides 30 dB of differential gain. Output voltage swing is adjustable up to 800 mVP-P differential by using the VAC analog control input. Additive rms jitter is less than 300 fs for 32 Gbps operation. HMC865LC3 has an internal DC offset correction circuit which provides differential 10 mVP-P input sensitivity.All input/output RF signals of the HMC865LC3 are terminated with 50 Ohms to +3.3V on chip and may be either AC or DC coupled. The outputs of the device can be operated either differentially or single-ended. Outputs can be connected directly to 50 Ohm terminated system referenced to 3.3V, while DC blocking capacitors may be used if the terminating system is 50 Ohms to a non 3.3V level.APPLICATIONS 100 Gbps Ethernet 100 Gbps Long Haul 40 Gbps (D)QPSK Receivers Broadband Gain Block for?Test & Measurement Equipment

The HMC877LC3 is a phase shifter/time delay with 0 to 500?(1.4 UI) continuously adjustable shift/delay range. The delay control is linearly monotonic with respect to the differential control voltage (VDCP, VDCN) and the control input has a modulation bandwidth of 2.5 GHz. The device provides a differential output voltage with constant amplitude for single-ended or differential input voltages above the input sensitivity level, while the output voltage swing may be adjusted using the VAC control pin. The HMC877LC3 features internal temperature compensation and bias circuitry to minimize delay variations with temperature. The device also features a delay control voltage range adjustment pin, LC. All RF input and outputs of the HMC877LC3 are internally terminated with 50 Ohms to VCC, and may either be AC or DC coupled. Output pins can be connected directly to a 50 Ohm to VCC terminated system, while DC blocking capacitors must be used if the terminated system input is 50 Ohms to a DC voltage other than VCC. The HMC877LC3 is available in ROHS-compliant 3 x 3 mm SMT package.APPLICATIONS Synchronization of Clock & Data Transponder Design Broadband Test & Measurement RF ATE Applications

The HMC954LC4B is a 2 to 1 Multiplexer designed for 32 Gbps data serialization. The mux latches the two differential inputs on a rising edge of the input clock. The device uses both rising and falling edges of the half-rate clock to serialize the data. The HMC954LC4B also features an output level control pin, VR, which allows for loss compensation or for signal-level optimization.All differential inputs to the HMC954LC4B are CML and terminated on-chip with 50 ??to the positive supply, GND, and may be AC or DC coupled. The differential CML outputs are source terminated to 50 ? and may also be AC or DC coupled. Outputs can be connected directly to a 50 ??ground-terminated system or drive devices with CML logic input. The HMC954LC4B operates from a single ?3.3 V supply and is available in a ceramic ROHS-compliant 4 ? 4 mm SMT package.APPLICATIONS SONET OC-192 Broadband Test &?Measurement Equipment FPGA Interfacing Circuitry 16 G and 32 G Fiber Channel 100 Gbit Ethernet

The HMC987LP5E 1-to-9 fanout buffer is designed for low noise clock distribution. It is intended to generate relatively square wave outputs with rise/fall times < 100 ps. The low skew and jitter outputs of the HMC987LP5E, combined with its fast rise/fall times, leads to controllable low-noise switching of downstream circuits such as mixers, ADCs/DACs or SERDES devices. The noise floor is particularly important in these applications, when the clocknetwork bandwidth is wide enough to allow squarewave switching. Driven at 2 GHz, outputs of the HMC987LP5E have a noise floor of ?166 dBc/Hz, corresponding to a jitter density of 0.6 asec/rtHz - or 50 fs over an 8 GHz bandwidth.The input stage can be driven single-ended or differentially, in a variety of signal formats (CML, LVDS, LVPECL or CMOS), AC or DC coupled. The input stage also features adjustable input impedance. It has 8 LVPECL outputs, and 1 CML output with adjustable swing/power-level in 3 dB steps.Individual output stages may be enabled or disabled for power-savings when not required using either hardware control pins, or under control of a serial-port interface.APPLICATIONS SONET, Fibre Channel,?GigE Clock Distribution ADC/DAC Clock Distribution Low Skew and Jitter Clock?or Data Fanout Wireless/Wired Communications Level Translation High Performance Instrumentation Medical Imaging Single-Ended to Differential?Conversion

The ADG5404 is a complementary metal-oxide semiconductor(CMOS) analog multiplexer, comprising four single channels.The on-resistance profile is very flat over the full analog input range, ensuring excellent linearity and low distortion when switching audio signals.The ADG5404 is designed on a trench process, which guardsagainst latch-up. A dielectric trench separates the P and Nchannel transistors, thereby preventing latch-up even undersevere overvoltage conditions.The ADG5404 switches one of four inputs to a common output,D, as determined by the 3-bit binary address lines, A0, A1, andEN. Logic 0 on the EN pin disables the device. Each switchconducts equally well in both directions when on and has aninput signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. All switchesexhibit break-before-make switching action.Product Highlights Trench Isolation Guards Against Latch-Up. A dielectric trench separates the P and N channel transistors, thereby preventing latch-up even under severe overvoltage conditions. Low RON. Dual-Supply Operation. For applications where the analog signal is bipolar, the ADG5404 can be operated from dual supplies of up to ?22 V. Single-Supply Operation. For applications where the analog signal is unipolar, the ADG5404 can be operated from a single-rail power supply of up to 40 V. 3 V logic-compatible digital inputs: VINH = 2.0 V, VINL = 0.8 V. No VL logic power supply required.Applications Relay replacement Automatic test equipment Data acquisition Instrumentation Avionics Audio and video switching Communication systems