The AD8366 is a matched pair of fully differential, low noise and low distortion, digitally programmable variable gain amplifiers (VGAs). The gain of each amplifier can be programmed separately or simultaneously over a range of 4.5 dB to 20.25 dB in steps of 0.25 dB. The amplifier offers flat frequency performance from dc to 70 MHz, independent of gain code.The AD8366 offers excellent spurious-free dynamic range, suitable for driving high resolution analog-to-digital converters (ADCs). The NF at maximum gain is 11.4 dB at 10 MHz and increases ~2 dB for every 4 dB decrease in gain. Over the entire gain range, the HD3/HD2 are better than ?90 dBc for 2 V p-p at the output at 10 MHz into 200 ?. The two-tone intermodulation distortion of ?90 dBc into 200 ? translates to an OIP3 of 45 dBm (38 dBVrms). The differential input impedance of 200 ? provides a well-defined termination. The differential output has a low impedance of ~25 ?.The output common-mode voltage defaults to VPOS/2 but can be programmed via the VCMA and VCMB pins over a range of voltages. The input common-mode voltage also defaults to VPOS/2 but can be driven down to 1.5 V. A built-in, dc offset compensation loop can be used to eliminate dc offsets from prior stages in the signal chain. This loop can also be disabled if dc-coupled operation is desired.The digital interface allows for parallel or serial mode gain programming. The AD8366 operates from a 4.75 V to 5.25 V supply and consumes typically 180 mA. When disabled, the part consumes roughly 3 mA. The AD8366 is fabricated using Analog Devices, Inc., advanced silicon-germanium bipolar process, and it is available in a 32-lead exposed paddle LFCSP package. Performance is specified over the ?40?C to +85?C temperature range.ApplicationsBaseband I/Q receiversDiversity receiversWideband ADC drivers?

The AD8417 is a high voltage, high resolution current shunt amplifier. It features an initial gain of 60 V/V, with a maximum ?0.3% gain error over the entire temperature range. The buffered output voltage directly interfaces with any typical converter. The AD8417 offers excellent input common-mode rejection from ?2 V to +70 V. The AD8417 performs bidirectional current measurements across a shunt resistor in a variety of automotive and industrial applications, including motor control, power management, and solenoid control.The AD8417 offers breakthrough performance throughout the ?40?C to +150?C temperature range. It features a zero drift core, which leads to a typical offset drift of 0.1 ?V/?C throughout the operating temperature range and the common-mode voltage range. The AD8417 is qualified for automotive applications. The device includes EMI filters and patented circuitry to enable output accuracy with pulse-width modulation (PWM) type input common-mode voltages. The typical input offset voltage is ?200 ?V. The AD8417 is offered in 8-lead MSOP and SOIC packages.Applications High-side current sensing in Motor controls Solenoid controls Power management Low-side current sensing Diagnostic protection

The AD8451 is a precision analog front end and controller for testing and monitoring battery cells. A precision fixed gain instrumentation amplifier (IA) measures the battery charge/discharge current, and a fixed gain difference amplifier (DA) measures the battery voltage. Internal laser trimmed resistor networks set the gains for the IA and the DA, optimizing the performance of the AD8451 over the rated temperature range. The IA gain is 26 and the DA gain is 0.8 V/V.Voltages at the ISET and VSET inputs set the desired constant current (CC) and constant voltage (CV) values. CC to CV switching is automatic and transparent to the system.A TTL logic level input, MODE, selects the charge or discharge mode (high for charge, low for discharge). An analog output, VCTRL, interfaces directly with the Analog Devices, Inc., ADP1972 PWM controller.The AD8451 simplifies designs by providing excellent accuracy, performance over temperature, flexibility with functionality, and overall reliability in a space-saving package. The AD8451 is available in an 80-lead, 14 mm ? 14 mm ? 1 mm LQFP package and is rated for an operating temperature of ?40?C to +85?C.APPLICATIONS Battery cell formation and testing Battery module testing

The AD8452-EVALZ is a platform for the AD8452, designed for investigation of the AD8452 analog and pulse-width modulation (PWM) features and performance without the added complications of a driver and/or switch mode power supply (SMPS) design. For convenience, a precision 5 V reference IC and four trim pots are built in to the evaluation board, for driving the battery current and voltage ISET and VSET inputs. All device pins are accessible with test loops or probe landings. At the same time, the AD8452-EVALZ has the flexibility to interface and drive a typical half bridge inductor input SMPS with output levels in the 1 A to 15 A range. SMPS and associated components are specified and sourced by the user. The AD8452 is intended for use as the core controller for commercial battery test and formation systems. Its advanced miniaturization and extraordinarily high level of analog precision meet the challenge of mass production of high energy density storage lithium ion packs for transportation and energy storage in homes. When working with the evaluation board, consult the AD8452 data sheet for a detailed device Theory of Operation and for additional information in conjunction with user guide UG-1180.

The?AD8494/AD8495/AD8496/AD8497?are precision instrumentation amplifiers with thermocouple cold junction compensators on an integrated circuit. They produce a high level (5 mV/?C) output directly from a thermocouple signal by combining an ice point reference with a precalibrated amplifier. They can be used as standalone thermometers or as switched output setpoint controllers using either a fixed or remote setpoint control.The AD8494/AD8495/AD8496/AD8497 can be powered from a single-ended supply (less than 3 V) and can measure temperatures below 0?C by offsetting the reference input. To minimize self-heating, an unloaded AD849x typically operates with a total supply current of 180 ?A, but it is also capable of delivering in excess of ?5 mA to a load.The AD8494 and AD8496 are precalibrated by laser wafer trimming to match the characteristics of J type (iron-constantan) thermocouples; the AD8495 and AD8497 are laser trimmed to match the characteristics of K type (chromel-alumel) thermo-couples. See Table 1 on the data sheet for the optimized ambient temperature range of each part.The AD8494/AD8495/AD8496/AD8497 allow a wide variety of supply voltages. With a 5 V single supply, the 5 mV/?C output allows the devices to cover nearly 1000 degrees of a thermo-couple?s temperature range.The AD8494/AD8495/AD8496/AD8497 work with 3 V supplies, allowing them to interface directly to lower supply ADCs. They can also work with supplies as large as 36 V in industrial systems that require a wide common-mode input range.Product Highlights Complete, precision laser wafer trimmed thermocouple signal conditioning system in a single IC package. Flexible pinout provides for operation as a setpoint controller or as a standalone Celsius thermometer. Rugged inputs withstand 4 kV ESD and provide over-voltage protection (OVP) up to VS ? 25 V. Differential inputs reject common-mode noise on the thermocouple leads. Reference pin voltage can be offset to measure 0?C on single supplies. Available in a small, 8-lead MSOP that is fully RoHS compliant.Applications K type thermocouple temperature measurement Setpoint controller Celsius thermometer Universal cold junction compensator White goods (oven, stove top) temperature measurements Exhaust gas temperature sensing Catalytic converter temperature sensing div#landing_page_sec ul { padding:0 0 15px 10px; margin:0px; } div#landing_page_sec li { padding:3px 0 2px 20px; margin:0px; list-style:none; background:url(/static/imported-files/embedded_html/images/li_img.gif) no-repeat 7px 9px; display:block; color:#000000; font-family: Arial, Helvetica, sans-serif; }

The AD9114/AD9115/AD9116/AD9117 are pin-compatible dual, 8-/10-/12-/14-bit, low power digital-to-analog converters (DACs) that provide a sample rate of 125 MSPS. These TxDAC? converters are optimized for the transmit signal path of communication systems. All the devices share the same interface, package, and pinout, providing an upward or downward component selection path based on performance, resolution, and cost.The AD9114/AD9115/AD9116/AD9117 offer exceptional ac and dc performance and support update rates up to 125 MSPS.The flexible power supply operating range of 1.8 V to 3.3 V and low power dissipation of the AD9114/AD9115/AD9116/AD9117 make them well suited for portable and low power applications.Product Highlights Low Power. DACs operate on a single 1.8 V to 3.3 V supply; total power consumption reduces to 225 mW at 100 MSPS. Sleep and power-down modes are provided for low power idle periods. CMOS Clock Input. High speed, single-ended CMOS clock input supports a 125 MSPS conversion rate. Easy Interfacing to Other Components. Adjustable output common mode from 0 V to 1.2 V allows for easy interfacing to other components that accept common-mode levels greater than 0 V.Applications Wireless infrastructures Picocell, femtocell base stations Medical instrumentation Ultrasound transducer excitation Portable instrumentation Signal generators, arbitrary waveform generators

The AD9125 is a dual, 16-bit, high dynamic range TxDAC+? digital-to-analog converter (DAC) that provides a sample rate of 1000 MSPS, permitting a multicarrier generation up to the Nyquist frequency. It includes features optimized for direct conversion transmit applications, including complex digital modulation, and gain and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators, such as the ADL537x F-MOD series from Analog Devices, Inc. A 4-wire serial port interface allows programming/readback of many internal parameters. Full-scale output current can be programmed over a range of 8.7 mA to 31.7 mA. The AD9125 comes in a 72-lead LFCSP.PRODUCT HIGHLIGHTS Ultralow noise and intermodulation distortion (IMD) enable high quality synthesis of wideband signals from baseband to high intermediate frequencies. A proprietary DAC output switching technique enhances dynamic performance. The current outputs are easily configured for various single-ended or differential circuit topologies. Flexible CMOS digital interface allows the standard 32-wire bus to be reduced to a 16-wire bus.APPLICATIONS Wireless infrastructure W-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM, LTE Digital high or low IF synthesis Transmit diversity Wideband communications: LMDS/MMDS, point-to-point Cable modem termination systems

The AD9148 is a quad, 16-bit, high dynamic range, digital-toanalogconverter (DAC) that provides a sample rate of 1000 MSPS.These devices include features optimized for direct conversiontransmit applications, including gain, phase, and offset compensation.The DAC outputs are optimized to interface seamlessly withanalog quadrature modulators such as the?ADL5371/ADL5372/ADL5373/ADL5374/ADL5375/. A serial peripheral interface (SPI)is provided for programming of the internal device parameters.Full-scale output current can be programmed over a range of 10 mAto 30 mA. The devices operate from 1.8 V and 3.3 V supplies fora total power consumption of 3 W at the maximum sample rate.They are enclosed in 196-ball chip scale package ball grid arraywith the option of an attached heat spreader..Product Highlights1. Low noise and inter-modulation distortion (IMD) enable highquality synthesis of wideband signals from baseband to highintermediate frequencies.2. A proprietary DAC output switching technique enhancesdynamic performance.3. The current outputs are easily configured for various singleendedor differential circuit topologies.4. LVDS data input interface includes FIFO to ease input timing.Applications Wireless infrastructure LTE, TD-SCDMA, WiMAX, WCDMA, CDMA2000, GSM MIMO/Transmit diversity Digital high or low IF synthesis

The AD91641 is a high performance, 16-bit digital-to-analog converter (DAC) and direct digital synthesizer (DDS) that supports update rates to 6 GSPS. The DAC core is based on a quad-switch architecture coupled with a 2? interpolator filter that enables an effective DAC update rate of up to 12 GSPS in some modes. The high dynamic range and bandwidth makes these DACs ideally suited for the most demanding high speed radio frequency (RF) DAC applications.The DDS consists of a bank of 32, 32-bit numerically controlled oscillators (NCOs), each with its own phase accumulator.When combined with a 100 MHz serial peripheral interface (SPI) and fast hop modes, phase coherent fast frequency hopping (FFH) is enabled, with several modes to support multiple applications.In baseband mode, wide analog bandwidth capability combines with high dynamic range to support DOCSIS 3.1 cable infrastructure compliance from the minimum of one carrier up to the full maximum spectrum of 1.791 GHz of signal bandwidth. A 2? interpolator filter (FIR85) enables the AD9164 to be configured for lower data rates and converter clocking to reduce the overall system power and ease the filtering requirements. In Mix-Mode? operation, the AD9164 can reconstruct RF carriers in the second and third Nyquist zones up to 7.5 GHz while still maintaining exceptional dynamic range. The output current can be programmed from 8 mA to 38.76 mA. The AD9164 data interface consists of up to eight JESD204B serializer/deserializer (SERDES) lanes that are programmable in terms of lane speed and number of lanes to enable application flexibility.An SPI interface configures the AD9164 and monitors the status of all registers. The AD9164 is offered in a 165-ball, 8 mm ? 8 mm, 0.5 mm pitch CSP_BGA package, and a 169-ball, 11 mm ? 11 mm, 0.8 mm pitch, CSP_BGA package, including a leaded ball option.Product Highlights High dynamic range and signal reconstruction bandwidth supports RF signal synthesis of up to 7.5 GHz. Up to eight lanes JESD204B SERDES interface flexible in terms of number of lanes and lane speed. Bandwidth and dynamic range to meet DOCSIS 3.1 compliance and multiband wireless communications standards with margin.?Applications Broadband communications systems DOCSIS 3.1 CMTS/ video on demand (VOD)/edge quadrature amplitude modulation (EQAM) Wireless communications infrastructure W-CDMA, LTE, LTE-A, point to point

The AD91641 is a high performance, 16-bit digital-to-analog converter (DAC) and direct digital synthesizer (DDS) that supports update rates to 6 GSPS. The DAC core is based on a quad-switch architecture coupled with a 2? interpolator filter that enables an effective DAC update rate of up to 12 GSPS in some modes. The high dynamic range and bandwidth makes these DACs ideally suited for the most demanding high speed radio frequency (RF) DAC applications.The DDS consists of a bank of 32, 32-bit numerically controlled oscillators (NCOs), each with its own phase accumulator.When combined with a 100 MHz serial peripheral interface (SPI) and fast hop modes, phase coherent fast frequency hopping (FFH) is enabled, with several modes to support multiple applications.In baseband mode, wide analog bandwidth capability combines with high dynamic range to support DOCSIS 3.1 cable infrastructure compliance from the minimum of one carrier up to the full maximum spectrum of 1.791 GHz of signal bandwidth. A 2? interpolator filter (FIR85) enables the AD9164 to be configured for lower data rates and converter clocking to reduce the overall system power and ease the filtering requirements. In Mix-Mode? operation, the AD9164 can reconstruct RF carriers in the second and third Nyquist zones up to 7.5 GHz while still maintaining exceptional dynamic range. The output current can be programmed from 8 mA to 38.76 mA. The AD9164 data interface consists of up to eight JESD204B serializer/deserializer (SERDES) lanes that are programmable in terms of lane speed and number of lanes to enable application flexibility.An SPI interface configures the AD9164 and monitors the status of all registers. The AD9164 is offered in a 165-ball, 8 mm ? 8 mm, 0.5 mm pitch CSP_BGA package, and a 169-ball, 11 mm ? 11 mm, 0.8 mm pitch, CSP_BGA package, including a leaded ball option.Product Highlights High dynamic range and signal reconstruction bandwidth supports RF signal synthesis of up to 7.5 GHz. Up to eight lanes JESD204B SERDES interface flexible in terms of number of lanes and lane speed. Bandwidth and dynamic range to meet DOCSIS 3.1 compliance and multiband wireless communications standards with margin.?Applications Broadband communications systems DOCSIS 3.1 CMTS/ video on demand (VOD)/edge quadrature amplitude modulation (EQAM) Wireless communications infrastructure W-CDMA, LTE, LTE-A, point to point

The AD9208 is a dual, 14-bit, 3 GSPS analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of direct sampling wide bandwidth analog signals of up to 5 GHz. The ?3 dB bandwidth of the ADC input is 9 GHz. The AD9208 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage referenceeases design considerations. The analog input and clock signals are differential inputs. The ADC data outputs are internally connected to four digital downconverters (DDCs) through a crossbar mux. Each DDC consists of up to five cascaded signalprocessing stages: a 48-bit frequency translator (numerically controlled oscillator (NCO)), and up to four half-band decimationfilters. The NCO has the option to select preset bands over the general-purpose input/output (GPIO) pins, which enables the selection of up to three bands. Operation of the AD9208 between the DDC modes is selectable via SPI-programmable profiles.In addition to the DDC blocks, the AD9208 has several functions that simplify the automatic gain control (AGC) function in acommunications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect control bits in Register 0x0245 of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoidan overrange condition at the ADC input. In addition to the fast detect outputs, the AD9208 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC.The user can configure the Subclasss 1 JESD204B-based high speed serialized output in a variety of one-lane, two-lane, four-lane, and eight-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multidevice synchronization is supported through the SYSREF? and SYNCINB? input pins.The AD9208 has flexible power-down options that allow significant power savings when desired. All of these features canbe programmed using a 3-wire serial port interface (SPI).The AD9208 is available in a Pb-free, 196-ball BGA, specified over the ?40?C to +85?C ambient temperature range. Thisproduct is protected by a U.S. patent.Note that throughout this data sheet, multifunction pins, such as FD_A/GPIO_A0, are referred to either by the entire pin name or by a single function of the pin, for example, FD_A, when only that function is relevant.Product Highlights Wide, input ?3 dB bandwidth of 9 GHz supports direct radio frequency (RF) sampling of signals up to about 5 GHz. Four integrated, wideband decimation filter and NCO blocks supporting multiband receivers. Fast NCO switching enabled through GPIO pins. A SPI controls various product features and functions to meet specific system requirements. Programmable fast overrange detection and signal monitoring. On-chip temperature dioide for system thermal management. 12mm ? 12mm 196-Lead BGAApplications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A Electronic test and measurement systems Phased array radar and electronic warfare DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers

The AD9211 is a 10-bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. The product operates at up to a 300 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a track-and-hold (T/H) and voltage reference, are included on the chip to provide a complete signal conversion solution.The ADC requires a 1.8 V analog voltage supply and a differential clock for full performance operation. The digital outputs are LVDS (ANSI-644) compatible and support either twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing.Fabricated on an advanced CMOS process, the AD9211 is available in a 56-lead LFCSP, specified over the industrial temperature range (?40?C to +85?C).PRODUCT HIGHLIGHTS High Performance?Maintains 60.1 dBFS SNR @ 300 MSPS with a 70 MHz input. Low Power?Consumes only 410 mW @ 300 MSPS. Ease of Use?LVDS output data and output clock signal allow interface to current FPGA technology. The on-chip reference and sample-and-hold provide flexibility in system design. Use of a single 1.8 V supply simplifies system power supply design. Serial Port Control?Standard serial port interface supports various product functions, such as data formatting, disabling the clock duty cycle stabilizer, power-down, gain adjust, and output test pattern generation. Pin-Compatible Family?12-bit pin-compatible family offered as AD9230.APPLICATIONS Wireless and wired broadband communications Cable reverse path Communications test equipment Radar and satellite subsystems Power amplifier linearization

The AD9217 is a single, 12-bit, 6 GSPS/10.25 GSPS, radio frequency (RF) analog-to-digital converter (ADC) with a 6.5 GHz input bandwidth. The AD9217 supports high dynamic range frequency and time domain applications requiring wide instantaneous bandwidth and low conversion error rates (CER).The AD9217 features a low latency, high speed, parallel CML output interface that supports full bandwidth operation with compatible FPGA/ASIC receivers. The AD9217 can be reconfigured to operate in native AD9213 mode for applications requiring additional digital processing and JESD204B output support. Refer to the AD9213 data sheet?when operating the AD9217 in AD9213 mode.The AD9217 achieves dynamic range and linearity performance while consuming 4.2 W typical. The device is based on an interleaved pipeline architecture and features a proprietary calibration and randomization technique that suppresses interleaving spurious artifacts into its noise floor. The linearity performance of the AD9217 is preserved by a combination of on-chip dithering and calibration, which results in excellent spurious-free performance over a wide range of input signal conditions.The AD9217 is offered in a 192-ball ball grid array (BGA) package and is specified over a junction temperature range of ?20?C to +115?C.

The AD9219 is a quad, 10-bit, 40/65 MSPS analog-to-digital con-verter (ADC) with an on-chip sample-and-hold circuit designedfor low cost, low power, small size, and ease of use. The productoperates at a conversion rate of up to 65 MSPS and is optimized foroutstanding dynamic performance and low power in applications where a small package size is critical.The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performanceoperation. No external reference or driver components arerequired for many applications.The ADC automatically multiplies the sample rate clock for theappropriate LVDS serial data rate. A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individual-channel power-down is supported and typically consumes less than 2 mW when all channels are disabled.The ADC contains several features designed to maximizeflexibility and minimize system cost, such as programmableclock and data alignment and programmable digital test patterngeneration. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user- defined test patterns entered via the serial port interface (SPI).The AD9219 is available in an RoHS compliant, 48-lead LFCSP. It is specified over the industrial temperature range of ?40?C to +85?C.Product Highlights Small Footprint. Four ADCs are contained in a small, space-saving package. Low power of 94 mW/channel at 65 MSPS. Ease of Use. A data clock output (DCO) is provided that operates at frequencies of up to 390 MHz and supports double data rate (DDR) operation. User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirements. Pin-Compatible Family. This includes the AD9287 (8-bit), AD9228 (12-bit), and AD9259 (14-bit). ApplicationsMedical imaging and nondestructive ultrasoundPortable ultrasound and digital beam-forming systemsQuadrature radio receiversDiversity radio receiversTape drivesOptical networkingTest equipment

The AD9234 is a dual, 12-bit, 1 GSPS/500 MSPS ADC. The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed for sampling wide bandwidth analog signals. The AD9234 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth buffered inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. Each ADC data output is internally connected to an optional decimate-by-2 block. The AD9234 has several functions that simplify the automatic gain control (AGC) function in a communications receiver.?The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. In addition to the fast detect outputs, the AD9234 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC.Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, or four-lane configurations, depending on the acceptable lane rate of the receiving logic device and the sampling rate of the ADC. Multiple device synchronization is supported through the SYSREF? and SYNCINB? input pins.The AD9234 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V to 3.3 V capable 3-wire SPI.The AD9234 is available in a Pb-free, 64-lead LFCSP and is specified over the ?40?C to +85?C industrial temperature range. This product is protected by a U.S. patent.Product Highlights Low power consumption analog core, 12-bit, 1.0 GSPS dual analog-to-digital converter (ADC) with 1.5 W per channel. Wide full power bandwidth supports IF sampling of signals up to 2 GHz. Buffered inputs with programmable input termination eases filter design and implementation. Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements. Programmable fast overrange detection. 9 mm ? 9 mm 64-lead LFCSP. Pin compatible with the AD9680 14-bit, 1 GSPS dual ADC.Applications Communications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE Point-to-point radio systems Digital predistortion observation path General-purpose software radios Ultrawideband satellite receiver Instrumentation (spectrum analyzers, network analyzers, integrated RF test solutions) Digital oscilloscopes High speed data acquisition systems DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers

The AD9257 is an octal, 14-bit, 40 MSPS and 65 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 65 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individual channel power-down is supported and typically consumes less than 2 mW when all channels are disabled.The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).The AD9257 is available in an RoHS-compliant, 64-lead LFCSP. It is specified over the industrial temperature range of ?40?C to +85?C. This product is protected by a U.S. patent. APPLICATIONS Medical imaging and nondestructive ultrasound Portable ultrasound and digital beam-forming systems Quadrature radio receivers Diversity radio receivers Optical networking Test EquipmentPRODUCT HIGHLIGHTS Small Footprint. Eight ADCs are contained in a small, space-saving package. Low Power of 55 mW/Channel at 65 MSPS with Scalable Power Options. Ease of Use. A data clock output (DCO) is provided that operates at frequencies of up to 455 MHz and supports double data rate (DDR) operation. User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirements. Pin Compatible with the AD9637 (12-Bit Octal ADC).

The AD9266 is a monolithic, single-channel 1.8 V supply,16-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digitalconverter (ADC). It features a high performance sample-and-holdcircuit and on-chip voltage reference.The product uses multistage differential pipeline architecturewith output error correction logic to provide 16-bit accuracy at80 MSPS data rates and to guarantee no missing codes over thefull operating temperature range.The ADC contains several features designed to maximizeflexibility and minimize system cost, such as programmableclock and data alignment and programmable digital test patterngeneration. The available digital test patterns include built-indeterministic and pseudorandom patterns, along with customuser-defined test patterns entered via the serial port interface (SPI).A differential clock input with a selectable internal 1-to-8 divideratio controls all internal conversion cycles. An optional duty cyclestabilizer (DCS) compensates for wide variations in the clock dutycycle while maintaining excellent overall ADC performance.The interleaved digital output data is presented in offset binary,gray code, or twos complement format. A DCO is provided toensure proper latch timing with receiving logic. Both 1.8 V and3.3 V CMOS levels are supported.The AD9266 is available in a 32-lead RoHS-compliant LFCSPand is specified over the industrial temperature range (?40?Cto +85?C).Product Highlights The AD9266 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families. The sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use. A standard serial port interface supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO and data output (D15_D14 to D1_D0) timing and offset adjustments, and voltage reference modes. The AD9266 is packaged in a 32-lead RoHS-compliant LFCSP that is pin compatible with the AD9609 10-bit ADC, the AD9629 12-bit ADC, and the AD9649 14-bit ADC, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 80 MSPS.Applications Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA Smart antenna systems Battery-powered instruments Handheld scope meters Portable medical imaging Ultrasound Radar/LIDAR PET/SPECT imaging

The AD9510 provides a multi-output clock distribution functionalong with an on-chip phase-locked loop (PLL) core. The designemphasizes low jitter and phase noise to maximize data converterperformance. Other applications with demanding phase noiseand jitter requirements also benefit from this device.The PLL section consists of a programmable reference divider(R); a low noise, phase frequency detector (PFD); a precisioncharge pump (CP); and a programmable feedback divider (N).By connecting an external voltage-controlled crystal oscillator(VCXO) or voltage-controlled oscillator (VCO) to the CLK2and CLK2B pins, frequencies of up to 1.6 GHz can be synchronizedto the input reference.There are eight independent clock outputs. Four outputs are lowvoltage positive emitter-coupled logic (LVPECL) at 1.2 GHz,and four are selectable as either LVDS (800 MHz) or CMOS(250 MHz) levels.Each output has a programmable divider that can be bypassedor set to divide by any integer up to 32. The phase of one clockoutput relative to another clock output can be varied by meansof a divider phase select function that serves as a coarse timingadjustment. Two of the LVDS/CMOS outputs feature programmabledelay elements with full-scale ranges up to 8 ns of delay.This fine tuning delay block has 5-bit resolution, giving 25possible delays from which to choose for each full-scale setting(Register 0x36 and Register 0x3A = 00000b to 11000b).The AD9510 is ideally suited for data converter clockingapplications where maximum converter performance isachieved by encode signals with subpicosecond jitter.The AD9510 is available in a 64-lead LFCSP and can be operatedfrom a single 3.3 V supply. An external VCO, which requires anextended voltage range, can be accommodated by connectingthe charge pump supply (VCP) to 5.5 V. The temperature rangeis ?40?C to +85?C.Applications Low jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, and mixed-signal front ends (MxFEs) High performance wireless transceivers High performance instrumentation Broadband infrastructure

The AD9511 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. The PLL section consists of a programmable reference divider (R); a low noise phase frequency detector (PFD); a precision charge pump (CP); and a programmable feedback divider (N). By connecting an external VCXO or VCO to the CLK2/CLK2B pins, frequencies up to 1.6 GHz may be synchronized to the input reference. There are five independent clock outputs. Three outputs are LVPECL (1.2 GHz), and two are selectable as either LVDS (800 MHz) or CMOS (250 MHz) levels.Each output has a programmable divider that may be bypassed or set to divide by any integer up to 32. The phase of one clock output relative to another clock output may be varied by means of a divider phase select function that serves as a coarse timing adjustment. One of the LVDS/CMOS outputs features a programmable delay element with full-scale ranges up to 10 ns of delay. This fine tuning delay block has 5-bit resolution, giving 32 possible delays from which to choose for each full-scale setting. The AD9511 is ideally suited for data converter clocking applications where maximum converter performance is achieved by encode signals with subpicosecond jitter. The AD9511 is available in a 48-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5.5 V. The temperature range is ?40?C to +85?C. APPLICATIONSLow jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDS, DDC, DUC, MxFEsHigh performance wireless transceiversHigh performance instrumentationBroadband infrastructure

The AD9515 features a two-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part.There are two independent clock outputs. One output is LVPECL, while the other output can be set to either LVDS or CMOS levels. The LVPECL output operates to 1.6 GHz. The other output operates to 800 MHz in LVDS mode and to 250 MHz in CMOS mode.Each output has a programmable divider that can be set to divide by a selected set of integers ranging from 1 to 32. The phase of one clock output relative to the other clock output can be set by means of a divider phase select function that serves as a coarse timing adjustment.The LVDS/CMOS output features a delay element with three selectable full-scale delay values (1.5 ns, 5 ns, and 10 ns), each with 16 steps of fine adjustment.The AD9515 does not require an external controller for operation or setup. The device is programmed by means of 11 pins (S0 to S10) using 4-level logic. The programming pins are internally biased to ? VS. The VREF pin provides a level of ? VS. VS (3.3 V) and GND (0 V) provide the other two logic levels.The AD9515 is ideally suited for data converter clocking applications where maximum converter performance is achieved by encode signals with subpicosecond jitter.The AD9515 is available in a 32-lead LFCSP and operates from a single 3.3 V supply. The temperature range is ?40?C to +85?C. APPLICATIONS Low jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers High performance instrumentation Broadband infrastructure ATE