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The AD9517-31 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 1.75 GHz to 2.25 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz can be used.The AD9517-3 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements.The AD9517-3 features four LVPECL outputs (in two pairs) and four LVDS outputs (in two pairs). Each LVDS output can be reconfigured as two CMOS outputs. The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz.For applications that require additional outputs, a crystal reference input, zero-delay, or EEPROM for automatic configuration at startup, the AD9520 and AD9522 are available. In addition, the AD9516 and AD9518 are similar to the AD9517 but have a different combination of outputs.Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow a range of divisions up to a maximum of 1024.The AD9517-3 is available in a 48-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5 V. A separate LVPECL power supply can be from 2.5 V to 3.3 V (nominal).The AD9517-3 is specified for operation over the industrial range of ?40?C to +85?C.APPLICATIONS Low jitter, low phase noise clock distribution 10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4 Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation 1 AD9517 is used throughout to refer to all the members of the AD9517 family. However, when AD9517-3 is used, it is referring to that specific member of the AD9517 family.

DC1449A: Demo Board for the LT8415 Ultralow Power Boost Converter with Dual Half-Bridge Switches.

Demonstration circuit 1349A is a polyphase 3-output step-down supply with tracking featuring the LTC3853EUJ. The input voltage range is 6.5V to 14V. For applications with narrow, 5V ±0.5V input range, the board has an optional resistor to tie the INTVCC pin to the VIN pin. The demo board provides three 15A outputs, with output voltages of 1.8V, 1.2V and 2.5V. The main features of the board include rail tracking, an internal 5V linear regulator for bias, RUN pins for each output, two PGOOD signals and a Mode selector that allow the converter to run in CCM, pulse skip or Burst Mode operation. Synchronization to an external clock is also possible through some minor component changes.

The PMP6797 reference design provides an isolated 20V at 4.5A from an 18V-30V input with greater than 94% efficiency. This design uses the UCC2897A active clamp controller with self-driven synchronous rectifiers.

Use and Handling of Semiconductor Packages With Electroless Nickel/Immersion Gold (ENIG) Pad Finishes Application Report

The ADRF5549 is a dual-channel, integrated, RF front-end multichip module designed for time division duplexing (TDD) applications that operates from 1.8 GHz to 2.8 GHz. The ADRF5549 is configured in dual channels with a cascading, two-stage, low noise amplifier (LNA) and a high power, silicon single-pole, double-throw (SPDT) switch.In high gain mode, the cascaded two-stage LNA and switch offer a low noise figure of 1.4 dB and a high gain of 35 dB with an output third-order intercept point (OIP3) of 32 dBm typical.In low gain mode, one stage of the two-stage LNA is in bypass mode providing 17 dB of gain at a lower current of 35 mA. In power-down mode, the LNAs are turned off, and the device draws 12 mA.In transmit operation, when RF inputs are connected to a termination pin (TERM-ChA or TERM-ChB), the switch provides a low insertion loss of 0.6 dB and handles a long-term evolution (LTE) full lifetime average (9 dB peak to average ratio (PAR)) of 40 dBm and 43 dBm for a 9 dB PAR LTE single event (ApplicationsWireless InfrastructureTDD massive multiple input and multiple output (MIMO) and active antenna systemsTDD-based communication systems

DN011 -- RF Module Testing using SmartRF Studio

The PMP5602 is a high side Buck" converter: able to supply 300W peak (30V @ 10A) for 2.5millisec: and 64millisec OFF (3.76% duty-cycle). The input voltage range is 40V to 60V."

This reference design utilizes the TPS65310A-Q1 device which is a power management unit ideally suited for camera or radar based vision system to support features like lane departure warning: collision avoidance systems: blindspot detection or night vision. Alongside ADAS end-equipment applications: this PMIC is also suitable for safety applications.

The AD7403 is a high performance, second-order, ?-? modulator that converts an analog input signal into a high speed, single-bit data stream, with on-chip digital isolation based on Analog Devices, Inc., iCoupler? technology. The AD7403 operates from a 5 V (VDD1) power supply and accepts a differential input signal of ?250 mV (?320 mV full-scale). The differential input is ideally suited to shunt voltage monitoring in high voltage applications where galvanic isolation is required.The analog input is continuously sampled by a high performance analog modulator, and converted to a ones density digital output stream with a data rate of up to 20 MHz. The original information can be reconstructed with an appropriate digital filter to achieve 88 dB signal to noise ratio (SNR) at ?78.1 kSPS. The serial input/output can use a 5 V or a 3 V supply (VDD2).The serial interface is digitally isolated. High speed complementary metal oxide semiconductor (CMOS) technology, combined with monolithic transformer technology, means the on-chip isolation provides outstanding performance characteristics, superior to alternatives such as optocoupler devices. The AD7403 device is offered in a 16-lead, wide-body SOIC package and has an operating temperature range of ?40?C to +125?C. The AD7403-8 device is offered in an 8-lead, wide-body SOIC package and has an operating temperature range of ?40?C to +105?C.Applications Shunt current monitoring AC motor controls Power and solar inverters Wind turbine inverters Data acquisition systems Analog-to-digital and opto-isolator replacements

This power supply design generates a 12V/100W isolated output from a standard 48V telecom input. An active clamp forward converter is controlled by the UCC2897A. The INA202 and an external PFET are used to provide a current limited 12V/4.5A output derived from the main 12V output of the forward converter. This power supply has a peak efficiency of over 94%.

This reference design demonstrate an 12V input 5A output RGB LED driver for DLP: which includes single DC/DC using TPS54620 to support 3 channel RGB LED driver with PWM dimming control