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This paper presents a method for utilizing the on-chip PWM generators on a TMS320C240 DSP for digital-to-analog (D/A) conversion. The method involves analog low-pass filtering the PWM signal to remove high frequency components leaving only the low-frequency content. Theoretical and experimental results are presented to quantify the achievable bit resolution. In addition analog low-pass filter

The input structure circuit of a successive-approximation register analog-to-digital converter (SAR ADC) in combination with the driving circuit forms a transfer function that can be used to determin

HF Antenna Cookbook HF Antenna Cookbook Technical Application Report (11-08-26-001) PDF ONLY

The HMC987LP5E 1-to-9 fanout buffer is designed for low noise clock distribution. It is intended to generate relatively square wave outputs with rise/fall times < 100 ps. The low skew and jitter outputs of the HMC987LP5E, combined with its fast rise/fall times, leads to controllable low-noise switching of downstream circuits such as mixers, ADCs/DACs or SERDES devices. The noise floor is particularly important in these applications, when the clocknetwork bandwidth is wide enough to allow squarewave switching. Driven at 2 GHz, outputs of the HMC987LP5E have a noise floor of ?166 dBc/Hz, corresponding to a jitter density of 0.6 asec/rtHz - or 50 fs over an 8 GHz bandwidth.The input stage can be driven single-ended or differentially, in a variety of signal formats (CML, LVDS, LVPECL or CMOS), AC or DC coupled. The input stage also features adjustable input impedance. It has 8 LVPECL outputs, and 1 CML output with adjustable swing/power-level in 3 dB steps.Individual output stages may be enabled or disabled for power-savings when not required using either hardware control pins, or under control of a serial-port interface.APPLICATIONS SONET, Fibre Channel,?GigE Clock Distribution ADC/DAC Clock Distribution Low Skew and Jitter Clock?or Data Fanout Wireless/Wired Communications Level Translation High Performance Instrumentation Medical Imaging Single-Ended to Differential?Conversion

The LT8301 is a micropower isolated flyback converter. By sampling the isolated output voltage directly from the primary-side flyback waveform, the part requires no third winding or opto-isolator for regulation. The output voltage is programmed with a single external resistor. Internal compensation and soft-start further reduce external component count. Boundary mode operation provides a small magnetic solution with excellent load regulation. Low ripple Burst Mode operation maintains high efficiency at light load while minimizing the output voltage ripple. A 1.2A, 65V DMOS power switch is integrated along with all high voltage circuitry and control logic into a 5-lead ThinSOT? package.The LT8301 operates from an input voltage range of 2.7V to 42V and can deliver up to 6W of isolated output power. The high level of integration and the use of boundary and low ripple burst modes result in a simple to use, low component count, and high efficiency application solution for isolated power delivery.Applications Isolated Telecom, Automotive, Industrial, Medical Power Supplies Isolated Auxiliary/Housekeeping Power Supplies

DC1449A: Demo Board for the LT8415 Ultralow Power Boost Converter with Dual Half-Bridge Switches.

TPS62300 3.6V ? 6.0V Input, Tiny DCDC Converter Reference Design for Stellaris

Hotswap circuits rely on the thermal capacitance of the series-limiting MOSFET to dissipate the large transient energy under current- or power-limit operation. The peakjunction temperature must be controlled in order to achieve a robust design. The constant-power MOSFET protection of the TPS2490 provides a simple method to useinformation provided by MOSFET manufacturers to determine peak junct

The PMP5089 reference design uses the UCC28600 green-mode controller to generate a 12V/40W regulated output. The quasi-resonant switching of the UCC28600 allows this low-cost design to achieve a maximum load efficiency is over 87%: while the no load losses are less than 250mW.

DC336A - Demo Board

There are three Full Compare Units in the Event Manager Module. Each Full Compare Unit has two associated PWM outputs. The time base for Full Compare Units is provided by GP Timer One.This application report presents applications of the Full Compare: up to six PWM three PWM plus three complemented PWM generation in symmetric mode.

The PMP4804 reference design provides 3.3V at 100W from a standard 48V telecom input with greater than 94% efficiency. This design uses the UCC2897A active clamp controller along with the CSD16401Q5A synchronous rectifiers. The circuit is built in an industry standard Quarter-Brick footprint.

Over the past few years electronic products and especially those which fall within the category ofConsumer Electronics have been significantly reduced in physical size and weight. This documentprovides information about the techniques used to mount CSP size components.