Description

AM654x and AM652x Sitara Arm applications processors are built to meet the complex processing needs of modern industry 4.0 embedded products.

The AM654x and AM652x devices combine four or two Arm Cortex-A53 cores with a dual Cortex-R5F MCU subsystem which includes features intended to help customers achieve their functional safety goals for their end products and three Gigabit industrial communications subsystems (PRU_ICSSG) to create a SoC capable of high-performance industrial controls with industrial connectivity and processing for functional safety applications. AM65xx is currently undergoing assessment to be certified by TÜV SÜD according to IEC 61508.

The four Cortex-A53 cores in the AM654x are arranged in two dual-core clusters with shared L2 memory to create two processing channels. The two Cortex-A53 cores in the AM652x are available in a single dual-core cluster and two single-core cluster options. Extensive ECC is included on on-chip memory, peripherals, and interconnect for reliability. The SoC as a whole includes features intended to help customers design systems that can achieve their functional safety goals (assessment pending with TÜV SÜD). Cryptographic acceleration and secure boot are available on some AM654x and AM652x devices in addition to granular firewalls managed by the DMSC.

Programmability is provided by the Arm Cortex-A53 RISC CPUs with Neon extension, and the dual Cortex-R5F MCU subsystem is available for general purpose use as two cores or it can be used in lockstep to help meet the needs of functional safety applications. The PRU_ICSSG subsystems can be used to provide up to six ports of industrial Ethernet such as Profinet IRT, TSN, Ethernet/IP or EtherCAT™ (among many others), or they can be used for standard Gigabit Ethernet connectivity.

TI provides a complete set of software and development tools for the Arm cores including Processor SDK Linux, Linux-RT, RTOS, and Android as well as C compilers and a debugging interface for visibility into source code execution. Applicable functional safety and security documentation will be made available to assist customers in developing their functional safety or security related systems.

Features:

• Processor Cores:
• Dual- or Quad-Core Arm^® Cortex^®-A53 Microprocessor Subsystem at up to 1.1 GHz
  • Up to two Dual-Core or two Single-Core Cortex-A53 Clusters with 512KB L2 Cache Including SECDED
  • Each A53 Core has 32KB L1 ICache and 32K L1 DCache
• Dual-Core Arm Cortex-R5F at up to 400 MHz
  • Supports Lockstep Mode
  • 16KB ICache, 16KB DCache, and 64KB RAM per R5F Core
• Industrial Subsystem:
• Three Gigabit Industrial Communication Subsystems (PRU_ICSSG)
  • Up to two 10/100/1000 Ethernet Ports per PRU_ICSSG
  • Supports Two SGMII Ports ⁽²⁾
  • Compatibility with 10/100Mb PRU-ICSS
  • 24× PWMs per PRU_ICSSG
    • Cycle-by-Cycle Control
    • Enhanced Trip Control
  • 18× Sigma-Delta Filters per PRU_ICSSG
    • Short Circuit Logic
    • Over-Current Logic
  • 6× Multi-Protocol Position Encoder Interfaces per PRU_ICSSG
• Memory Subsystem:
• Up to 2MB of On-Chip L3 RAM with SECDED
• Multi-Core Shared Memory Controller (MSMC)
  • Up to 2MB (2 banks × 1MB) SRAM with SECDED
    • Shared Coherent Level 2 or Level 3 Memory-Mapped SRAM
    • Shared Coherent Level 3 Cache
  • 256-Bit Processor Port Bus and 40-Bit Physical Address Bus
  • Coherent Unified Bi-Directional Interfaces to Connect to Processors or Device Masters
  • L2, L3 Cache Pre-Warming and Post Flushing
  • Bandwidth Management with Starvation Bound
  • One Infrastructure Master Interface
  • Single External Memory Master Interface
  • Supports Distributed Virtual System
  • Supports Internal DMA Engine – DRU (Data Routing Unit)
  • ECC Error Protection
• DDR Subsystem (DDRSS)
  • Supports DDR3L/DDR4 Memory Types up to DDR-1600
  • Supports LPDDR4 Memory Type up to DDR-1333
  • 32-Bit Data Bus and 7-Bit SECDED Bus
  • 32GB of Total Addressable Space
• General-Purpose Memory Controller (GPMC)
• SafeTI™ Semiconductor Component:
• Designed for Functional Safety Applications
• Developed according to the requirements of IEC 61508
• Achieves systematic integrity of SIL-3
• For the MCU Safety Island, sufficient diagnostics are included to achieve random fault integrity requirements of SIL-3
• For the rest of the SoC, sufficient diagnostics are included to achieve random fault integrity requirements of SIL-2
  • In addition, sufficient architectural metrics are in place to achieve execution of SIL-3 applications given a proper safety concept (e.g. Reciprocal Comparison by Software)
• Functional Safety Manual Available
• Safety-Related Certification
  • Component level functional safety certification by TÜV SÜD [Certification in progress]
• Functional Safety Features:
  • ECC or Parity on Calculation-Critical Memories and Internal Bus Interconnect
  • Firewalls to Help Provide Freedom From Interference (FFI)
    • Built-In Self-Test (BIST) for CPU, High-End Timers, and On-Chip RAM
  • Hardware Error Injection Support for Test-for-Diagnostics
  • Error Signaling Modules (ESM) for Capture of Functional Safety Related Errors
  • Voltage, Temperature, and Clock Monitoring
  • Windowed and Non-Windowed Watchdog Timers in Multiple Clock Domains
• MCU Island
  • Isolation of the Dual-Core Arm Cortex-R5F Microprocessor Subsystem
  • Separate Voltage, Clocks, Resets, and Dedicated Peripherals
  • Internal MCSPI Connection to the Rest of SoC
• Security:
• Secure Boot Supported
  • Hardware-Enforced Root-of-Trust
  • Support to Switch Root-of-Trust via Backup Key
  • Support for Takeover Protection, IP Protection, and Anti-Roll Back Protection
• Cryptographic Acceleration Supported
  • Session-Aware Cryptographic Engine with Ability to Auto-Switch Key-Material Based on Incoming Data Stream
  • Supports Cryptographic Cores
    • AES – 128/192/256 Bits Key Sizes
    • 3DES – 56/112/168 Bits Key Sizes
    • MD5, SHA1
    • SHA2 – 224/256/384/512
    • DRBG with True Random Number Generator
    • PKA (Public Key Accelerator) to Assist in RSA/ECC Processing
  • DMA Support
• Debugging Security
  • Secure Software Controlled Debug Access
  • Security Aware Debugging
• Trusted Execution Environment (TEE) Supported
  • Arm TrustZone^® Based TEE
  • Extensive Firewall Support for Isolation
  • Secure DMA Path and Interconnect
  • Secure Watchdog/Timer/IPC
• Secure Storage Support
• On-the-Fly Encryption and Authentication Support for OSPI Interface
• Networking Security Support for Data (Payload) Encryption/Authentication via Packet Based Hardware Cryptographic Engine
• Security Co-Processor (DMSC) for Key and Security Management, with Dedicated Device Level Interconnect for Security
• SoC Services:
• Device Management Security Controller (DMSC)
  • Centralized SoC System Controller
  • Manages System Services Including Initial Boot, Security, Functional Safety and Clock/Reset/Power Management
  • Power Management Controller for Active and Low Power Modes
  • Communication with Various Processing Units over Message Manager
  • Simplified Interface for Optimizing Unused Peripherals
  • Tracing and Debugging Capability
• Sixteen 32-Bit General-Purpose Timers
• Two Data Movement and Control Navigator Subsystems (NAVSS)
  • Ring Accelerator (RA)
  • Unified DMA (UDMA)
  • Up to 2 Timer Managers (TM) (1024 Timers Each)
• Multimedia:
• Display Subsystem
  • Two Fully Input-Mapped Overlay Managers Associated with Two Display Outputs
  • One Port MIPI^® DPI Parallel Interface
  • One Port OLDI
• Graphics Processing Unit (GPU)
• One Camera Serial Interface-2 (MIPI CSI-2)
• One Port Video Capture: BT.656/1120 (No Embedded Sync)
• High-Speed Interfaces:
• One Gigabit Ethernet (CPSW) Interface Supporting
  • RMII (10/100) or RGMII (10/100/1000)
  • IEEE1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP
  • Audio/Video Bridging (P802.1Qav/D6.0)
  • Energy-Efficient Ethernet (802.3az)
  • Jumbo Frames (2024 bytes)
  • Clause 45 MDIO PHY Management
• Two PCI-Express^® Revision 3.1 Subsystems ⁽²⁾
  • Supports Gen3 (8.0GT/s) Operation
  • Two Independent 1-lane, or a Single 2-lane Port
  • Support for Concurrent Root-Complex and/or End-Point Operation
• USB 3.1 Dual-Role Device Subsystem ⁽²⁾
  • One Enhanced SuperSpeed Gen1 Port
  • One USB 2.0 Port
  • Each Port Independently Configurable as USB Host, USB Peripheral, or USB Dual-Role Device
• General Connectivity:
• 6× Inter-Integrated Circuit (I2C) Ports
• 5× Configurable UART/IrDA/CIR Modules
• Two Simultaneous Flash Interfaces Configured
  • Two OSPI™ Flash Interfaces
  • or Hyperbus™ and OSPI1 Flash Interface
• 2× 12-Bit Analog-to-Digital Converters (ADC)
  • Up to 4 Msamples/s
  • Eight Multiplexed Analog Inputs
• 8× Multichannel Serial Peripheral Interfaces (MCSPI) Controllers
  • Two with Internal Connections
  • Six with External Interfaces
• General-Purpose I/O (GPIO) Pins
• Control Interfaces:
• 6× Enhanced High Resolution Pulse-Width Modulator (EHRPWM) Modules
• One Enhanced Capture (eCAP) Module
• 3× Enhanced Quadrature Encoder Pulse (eQEP) Modules
• Automotive Interfaces:
• 2× Modular Controller Area Network (MCAN) Modules with Full CAN-FD Support
• Audio Interfaces:
• 3× Multichannel Audio Serial Port (MCASP) Modules
• Media and Data Storage:
• 2× MultiMedia Card/Secure Digital (MMC/SD) Interfaces
• Simplified Power Management:
• Simplified Power Sequence with Full Support for Dual Voltage I/O
• Integrated LDOs Reduces Power Solution Complexity
• Integrated SDIO LDO for Handling Automatic Voltage Transition for SD Interface
• Integrated POR (Power on Reset) Generation Reducing Power Solution Complexity
• Integrated Voltage Supervisor for Functional Safety Monitoring
• Integrated Power Supply Glitch Detector for Detecting Fast Power Supply Transients
• Analog/System Integration:
• Integrated USB VBUS Detection
• Fail Safe I/O for DDR RESET
• All I/O Pins Drivers Disabled During Reset to Avoid Bus Conflicts
• Default I/O Pulls Disabled During Reset to Avoid System Conflicts
• Support Dynamic I/O Pinmux Configuration Change
• System on Chip (SoC) Architecture:
• Supports Primary Boot from UART, I2C, MCSPI, HyperBus, Parallel NOR Flash, SD or eMMC, USB, PCIe, and Ethernet Interfaces
• 28-nm CMOS Technology
• 23 mm × 23 mm, 0.8-mm Pitch, 784-Pin S-PBGA (ACD)