Current Sense Amplifier 1 Circuit 8-SO

LT1374-SYNC series DC/DC, Step Down 1, Non-Isolated Outputs Evaluation Board

A2B Main 4xPDM XCVR wI2S/TDM Features:A2B BUS FEATURES Line topology Single main node, multiple subordinate nodes Up to 15 m between nodes and up to 40 m overall cable length Communication over distance Synchronous data Multichannel I2S/TDM to I2S/TDM Synchronous clock, phase aligned in all nodes Low latency node to node communication Control and status information I2C to I2C GPIO and interrupt Bus power or local power subordinate nodes Configurable with SigmaStudio/SigmaStudio+ graphical software tool AEC-Q100 qualified for automotive applicationsA2B TRANSCEIVER FEATURES Configurable A2B bus main node or subordinate node Programmable via I2C interface 8-bit to 32-bit multichannel I2S/TDM interface Programmable I2S/TDM data rate Up to 32 upstream and 32 downstream channels PDM interface Programmable PDM clock rate Up to 4 high dynamic range microphone inputs Simultaneous reception of I2S data with up to 4 PDM microphones Unique ID register for each transceiver Crossover or straight-through cabling Programmable settings to optimize EMC performance

Variable Resolution Resolver-to-Digital Converter Features: Tracking R/D Converter High Accuracy Velocity Output High Max Tracking Rate 1040 RPS (10 Bits) 44-Lead PLCC Package 10-, 12-, 14-, or 16-Bit Resolution Set by User Ratiometric Conversion Stabilized Velocity Reference Dynamic Performance Set by User Industrial Temperature Range

18-Bit, 2 MSPS/1 MSPS/500 kSPS, Precision, Pseudo Differential, SAR ADCs Features: Easy Drive Greatly reduced input kickback Input current reduced to 0.5 μA/MSPS Enhanced acquisition phase, ≥79% of cycle time at 1 MSPS First conversion accurate, no latency or pipeline delay Input span compression for single-supply operation Fast conversion allows low SPI clock rates Input overvoltage clamp protection sinks up to 50 mA SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface High performance Pseudo differential analog input range 0 V to VREF with VREF from 2.4 V to 5.1 V Throughput: 2 MSPS/1 MSPS/500 kSPS options INL: ±3.2 LSB maximum Guaranteed 18-bit, no missing codes SNR: 95 dB at fIN = 1 kHz at VREF = 5 V THD: −125 dB at fIN = 1 kHz, −108 dB at fIN = 100 kHz SINAD: 84.5 dB at fIN = 1 MHz (see Figure 17 in data sheet) Oversampled dynamic range 98 dB for OSR = 2 125 dB for OSR = 1024 Low power Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface 2.5 mW at 500 kSPS (VDD only) 70 μW at 10 kSPS, 14 mW at 2 MSPS (total power) 10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP Pin compatible with AD4003/AD4007/AD4011 family Guaranteed operation: −40°C to +125°C

18-Bit, 2 MSPS/1 MSPS/500 kSPS, Precision, Pseudo Differential, SAR ADCs Features: Easy Drive Greatly reduced input kickback Input current reduced to 0.5 μA/MSPS Enhanced acquisition phase, ≥79% of cycle time at 1 MSPS First conversion accurate, no latency or pipeline delay Input span compression for single-supply operation Fast conversion allows low SPI clock rates Input overvoltage clamp protection sinks up to 50 mA SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface High performance Pseudo differential analog input range 0 V to VREF with VREF from 2.4 V to 5.1 V Throughput: 2 MSPS/1 MSPS/500 kSPS options INL: ±3.2 LSB maximum Guaranteed 18-bit, no missing codes SNR: 95 dB at fIN = 1 kHz at VREF = 5 V THD: −125 dB at fIN = 1 kHz, −108 dB at fIN = 100 kHz SINAD: 84.5 dB at fIN = 1 MHz (see Figure 17 in data sheet) Oversampled dynamic range 98 dB for OSR = 2 125 dB for OSR = 1024 Low power Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface 2.5 mW at 500 kSPS (VDD only) 70 μW at 10 kSPS, 14 mW at 2 MSPS (total power) 10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP Pin compatible with AD4003/AD4007/AD4011 family Guaranteed operation: −40°C to +125°C

18-Bit, 2 MSPS/1 MSPS/500 kSPS, Precision, Pseudo Differential, SAR ADCs Features: Easy Drive Greatly reduced input kickback Input current reduced to 0.5 μA/MSPS Enhanced acquisition phase, ≥79% of cycle time at 1 MSPS First conversion accurate, no latency or pipeline delay Input span compression for single-supply operation Fast conversion allows low SPI clock rates Input overvoltage clamp protection sinks up to 50 mA SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface High performance Pseudo differential analog input range 0 V to VREF with VREF from 2.4 V to 5.1 V Throughput: 2 MSPS/1 MSPS/500 kSPS options INL: ±3.2 LSB maximum Guaranteed 18-bit, no missing codes SNR: 95 dB at fIN = 1 kHz at VREF = 5 V THD: −125 dB at fIN = 1 kHz, −108 dB at fIN = 100 kHz SINAD: 84.5 dB at fIN = 1 MHz (see Figure 17 in data sheet) Oversampled dynamic range 98 dB for OSR = 2 125 dB for OSR = 1024 Low power Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface 2.5 mW at 500 kSPS (VDD only) 70 μW at 10 kSPS, 14 mW at 2 MSPS (total power) 10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP Pin compatible with AD4003/AD4007/AD4011 family Guaranteed operation: −40°C to +125°C

24-Bit, 2 MSPS, SAR ADC Features: High performance Throughput: 2 MSPS maximum INL: ±0.9 ppm maximum from −40°C to +125°C SNR: 108.4 dB typical THD: −127 dB typical NSD: −169 dBFS/Hz typical Low power 30 mW at 2 MSPS 3 mW at 10 kSPS Easy Drive™ features reduce system complexity Low 1.2 μA input current for dc inputs Wide input common-mode range: −(1/128) × VREF to +(129/128) × VREF Flexible external reference voltage range: 4.096 V to 5 V Accurate integrated reference buffer with 2 μF bypass capacitor Programmable block averaging filter with up to 216 decimation Extended sample resolution to 30 bits Overrange and synchronization bits Flexi-SPI digital interface 1, 2, or 4 SDO lanes allows slower SCK Echo clock mode simplifies use of digital isolator Compatible with 1.2 V to 1.8 V logic 7 mm × 7 mm 64-Ball CSP_BGA package with internal supply and reference capacitors to help reduce system footprint

Universal Input Analog Front End with 24-Bit ADC for Industrial Process Control Systems Features: 2 software programmable input terminals Current up to ±20 mA Voltage up to ±10 V Thermocouple RTD Replaces existing 3-terminal solutions Field power supply for loop powered current sensors HV input overvoltage protected up to ±30 V Internal current sense resistor Option to use external current sense resistor Current limited input even with no power supply Diagnostic functions for overrange and open wire detect Fast and flexible output data rates: 5 SPS to 125 kSPS 16 noise free bits at 62 kSPS 18 noise free bits at 2.5 kSPS 20 noise free bits at 50 SPS/60 SPS Simultaneous 50 Hz and 60 Hz rejection Serial interface for configuration and diagnostics 4-wire interface compatible with SPI®, QSPI™, MICROWIRE®, and DSP Power supply: ±12 V to ±20 V, +5 V Operating temperature: −40°C to +105°C Package: 40-lead, 6 mm × 6 mm LFCSP

Single Supply, 24-Bit, Sigma-Delta ADC with 10 V and 0 mA to 20 mA Inputs, Open Wire Detection Features: Tested for robustness per: IEC6100-4-2, IEC6100-4-3, IEC6100-4-4, IEC6100-4-5, IEC6100-4-6, CISPR 11 24-bit ADC with integrated analog front end Fast and flexible output rate: 1.25 SPS to 31.25 kSPS Channel scan data rate of 6.21 kSPS per channel (161 μs settling) 16 noise free bits at 1 kSPS per channel 85 dB rejection of 50 Hz and 60 Hz at 20 SPS per channel ±10 V inputs, 4 differential or 8 single-ended Pin absolute maximum rating ±50 V Absolute input pin voltage up to ±20 V ≥1 MΩ impedance ±0.06% accuracy at 25°C Open wire detection 0 mA to 20 mA inputs, 4 single-ended Pin absolute maximum rating ±50 mA Input range from −0.5 mA to +24 mA 60 Ω impedance ±0.08% accuracy at 25°C On-chip 2.5 V reference ±0.12% accuracy at 25°C, ±5 ppm/°C (typical) drift Internal or external clock Power supplies AVDD = 3.0 V to 5.5 V IOVDD = 2 V to 5.5 V Total IDD = 3.9 mA Temperature range: −40°C to +105°C 3-wire or 4-wire serial digital interface (Schmitt trigger on SCLK) SPI, QSPI, MICROWIRE, and DSP compatible

Single-Supply, Multichannel, 125 kSPS, 24-Bit, Sigma-Delta ADC with 10 V Inputs Features:24-bit ADC with integrated AFEFast and flexible output rate: 2.5 SPS to 125 kSPSChannel scan data rate of 24,845 SPS per channel (40.25 s settling)85 dB common mode rejection of 50 Hz and 60 Hz at 20 SPS per channel10 V inputs, either 8 differential or 16 single-endedVIN pin absolute maximum rating 65 VAbsolute input pin voltage up to 20 VMinimum 1 M impedanceOn-chip 2.5 V reference0.12% initial accuracy at 25C, 5 ppm/C (typical) driftInternal or external clockPower suppliesAVDD = 4.5 V to 5.5 VIOVDD = 2 V to 5.5 VTotal current consumption AVDD + IOVDD (IDD) = 10.4 mATemperature range: 40C to +105C3-wire or 4-wire serial digital interface (Schmitt trigger on SCLK)SPI, QSPI, MICROWIRE, and DSP compatible

16-Bit, 2 MSPS, Dual Channel SAR ADC Features: High performance Throughput: 2 MSPS per channel maximum INL: ±3 ppm maximum from −40°C to +125°C SNR: 97.4 dB typical THD: −127 dB typical NSD: −157.4 dBFS/Hz typical Low power 15 mW per channel at 2 MSPS 1.5 mW per channel at 10 kSPS Easy Drive features reduce system complexity Low 0.6 μA input current for dc inputs Wide common-mode input range: −(1/128) × VREF to +(129/128) × VREF Flexible external reference voltage range: 4.096 V to 5 V Accurate integrated reference buffer with 2 μF bypass capacitor Programmable block averaging filter with up to 216 decimation Extended sample resolution to 30 bits Over range and synchronization bits Flexi-SPI digital interface 1, 2, or 4 SDO lanes per channel allows slower SCK Echo clock mode simplifies use of digital isolator Compatible with 1.2 V to 1.8 V logic 7 mm × 7 mm 64-Ball CSP_BGA package with internal supply and reference capacitors to help reduce system footprint

Differential Inputs, 1 MSPS, Dual Simultaneous Sampling SAR ADCs Features: 16-bit ADC family Dual simultaneous sampling Fully differential analog inputs Throughput conversion rate 1 MSPS for AD4680 500 kSPS for AD4681 SNR (typical) 92.5 dB, VREF = 3.3 V external 100 dB with 8× OSR, RES = 1 On-chip oversampling function Resolution boost function INL (maximum) 1.5 LSBs 2.5 V internal reference at 10 ppm/°C High speed serial interface −40°C to +125°C operation 3 mm × 3 mm, 16-lead LFCSP Wide common-mode range Alert function

Differential Inputs, 500 kSPS, Dual Simultaneous Sampling SAR ADCs Features: 16-bit ADC family Dual simultaneous sampling Fully differential analog inputs Throughput conversion rate 1 MSPS for AD4680 500 kSPS for AD4681 SNR (typical) 92.5 dB, VREF = 3.3 V external 100 dB with 8× OSR, RES = 1 On-chip oversampling function Resolution boost function INL (maximum) 1.5 LSBs 2.5 V internal reference at 10 ppm/°C High speed serial interface −40°C to +125°C operation 3 mm × 3 mm, 16-lead LFCSP Wide common-mode range Alert function

16-Bit, 8-Channel, 500 kSPS, Easy Drive Multiplexed SAR ADC Features: Easy Drive Reduced analog input and reference drive requirements On-chip reference buffer (WLCSP only) Overvoltage protection up to 5 mA on each analog input Long acquisition phase, ≥71.5% (715 ns/1000 ns) of cycle time at 1 MSPS High performance Sample rate: 500 kSPS (AD4697) or 1 MSPS (AD4698) INL: ±1 LSB maximum Guaranteed 16-bit, no missing codes SINAD: 93 dB typical, fIN = 1 kHz Oversampled dynamic range: 111.2 dB, OSR = 64 Small footprint, high channel density 24-lead, 4.00 mm × 4.00 mm LFCSP 36-lead, 2.960 mm × 2.960 mm WLCSP Easy Drive features support system level designs with fewer components Enhanced digital functionality First conversion accurate, no latency or pipeline delay Fast conversion time and dual-/quad-SDO modes allow low SPI clock rates Customizable channel sequencer On-chip oversampling and decimation Threshold detection alerts Offset and gain correction Autonomous conversion (autocycle) mode 1.14 V to 1.98 V logic SPI Low power 8 mW at fS = 1 MSPS and 4 mW at fS = 500 kSPS 4 μW standby power dissipation with the internal LDO disabled Internal LDO enables 3.15 V to 5.5 V, single analog supply operation Wide operating temperature range: −40°C to +125°C

Fully Accurate 12-Bit VOUT nanoDAC SPI Interface 4.5 V to 5.5 V in a TSSOP Features: Low power dual 12-/14-/16-bit DAC, ±1 LSB INL Individual voltage reference pins Rail-to-rail operation 4.5 V to 5.5 V power supply Power-on reset to zero scale or midscale Power down to 400 nA at 5 V 3 power-down functions Per channel power-down Low glitch upon power-up Hardware power-down lockout capability Hardware LDAC with software LDAC override function CLR function to programmable code SDO daisy-chaining option 14-lead TSSOP

Dual Channel, 128-Position, I2C, Nonvolatile Digital Potentiometer Features: 10 kΩ and 100 kΩ resistance options Resistor tolerance: 8% maximum Wiper current: ±6 mA Low temperature coefficient: 35 ppm/°C Wide bandwidth: 3 MHz Fast start-up time < 75 μs Linear gain setting mode Single- and dual-supply operation Independent logic supply: 1.8 V to 5.5 V Wide operating temperature: −40°C to +125°C 3 mm × 3 mm package option Qualified for automotive applications

Quad Channel, 128-Position, SPI, Nonvolatile Digital Potentiometer Features: 10 kΩ and 100 kΩ resistance options Resistor tolerance: 8% maximum Wiper current: ±6 mA Low temperature coefficient: 35 ppm/°C Wide bandwidth: 3 MHz Fast start-up time < 75 μs Linear gain setting mode Single- and dual-supply operation Independent logic supply: 1.8 V to 5.5 V Wide operating temperature: −40°C to +125°C 4 mm × 4 mm package option

256 Position SPI/I2C Selectable Digital Potentiometer Features: 256-position End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Compact MSOP-10 (3 mm × 4.9 mm) package Pin selectable SPI/I2C compatible interface Extra package address decode pin AD0 Full read/write of wiper register Power-on preset to midscale Single supply 2.7 V to 5.5 V Low temperature coefficient 45 ppm/°C Low power, IDD = 8 μA Wide operating temperature −40°C to +125°C SDO output allows multiple device daisy-chaining Evaluation board available

Nonvolatile, Quad, 64-Position Digital Potentiometer Features: Nonvolatile Memory Preset Maintains Wiper Settings 4-channel independent programmable 64-position resolution EEMEM restore time: 140 μs typical Full monotonic operation 10 kΩ, 50 kΩ, and 100 kΩ terminal resistance See Data Sheet for Additional Information