Configurable Impedance Network Analyzer & Potentiostat with Integrated Cortex M3 Core Features: Analog performance 160 kSPS, 16-bit, precision analog-to-digital converter (ADC) 4 dedicated voltage measurement channels 8 current measurement channels Impedance measurement engine High precision voltage reference Supply noise rejection filtering Ultralow leakage configurable switch matrix 12-bit digital-to-analog converter (DAC) Precision instrumentation amplifier control loop 6-channel CapTouch controller Temperature sensor Analog hardware accelerators Autonomous analog front-end (AFE) controller Independent sequencer for AFE functions Direct digital synthesizer (DDS)/arbitrary waveform generator Receive filters Complex impedance measurement (DFT) engine Processing 16 MHz ARM Cortex-M3 processor 384 kB of embedded flash memory 32 kB system SRAM 16 kB Flash configured EEPROM Integrated full-speed USB 2.0 controller and PHY Multilayer advanced microcontroller bus architecture (AMBA) bus matrix Central direct memory access (DMA) controller Real-time clock (RTC) General-purpose, wake-up, and watchdog timers Communication Input/output I2S and beeper interface LCD display controller (parallel and serial) LCD segment controller SPI, I2C, and UART peripheral interfaces Programmable GPIOs Power Coin cell battery compatible 2.5 V to 3.6 V active measurement range Power management unit (PMU) Power-on reset (POR) and power supply monitor (PSM) Packages and temperature range Operating temperature range: −40°C to +85°C Package: 120-lead, 8 mm × 8 mm CSP_BGA 

16-Bit, Isolated Sigma-Delta Modulator Features: 5 MHz to 21 MHz master clock input frequency Offset drift vs. temperature: ±0.6 μV/°C maximum SNR: 86 dB typical 16 bits, no missing codes Full-scale analog input voltage range: ±320 mV ENOB: 14 bits typical IDD1: 10 mA maximum On-board digital isolator Operating temperature range: −40°C to +125°C High common-mode transient immunity: 150 kV/μs minimum, VDD2 = 3.3 V Wide-body SOICs 16-lead SOIC_W 8-lead SOIC_IC with increased creepage Safety and regulatory approvals (pending) UL recognition 5700 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice SA VOE Certificate of Conformity DIN V VDE V 0884-10 VlORM = 1270 VPEAK DIN V VDE V 0884-11 VlORM = 1060 VPEAK

16-Bit, Isolated, Sigma-Delta ADC Features: 5 MHz to 21 MHz master clock input frequency Offset drift vs. temperature: ±0.6 μV/°C maximum SNR: 86 dB typical 16 bits, no missing codes Full-scale analog input voltage range: ±320 mV ENOB: 14 bits typical IDD1: 10 mA maximum On-board digital isolator Operating temperature range −40°C to +125°C (16-lead SOIC_W) −40°C to +105°C (8-lead SOIC_IC) 20 V operation on VDD1 High CMTI: 150 kV/μs minimum, VDD2 = 3.3 V Wide-body SOICs 16-lead SOIC_W 8-lead SOIC_IC with increased creepage Safety and regulatory approvals UL recognition 5700 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice 5A (Pending) VDE Certificate of Conformity DIN V VDE V 0884-10: VIORM = 1270 VPEAK DIN V VDE V 0884-11: VIORM = 1060 VPEAK (Pending)

67 dB SMT SDLVA, 0.5 - 18.5 GHz Features: High Logging Range: 67 dB (-62 to +5 dBm) Output Frequency Flatness: ±2 dB Log Linearity: ±2 dB Fast Rise/Fall Times: 5/15 ns Single Positive Supply: +3.3V ESD Sensitivity (HBM): Class 1A 24 Lead 4x4mm SMT Package: 16mm2

Dual RMS Power Detector SMT, Single-Ended, DC - 3.9 GHz Features: Crest Factor (Peak-to-Average Power Ratio) Measurement ±1 dB Detection Accuracy to 3.9 GHz Input Dynamic Range: -55 dBm to +15 dBm RF Signal Wave Shape & Crest Factor Independent +5V Operation from -40° C to +85° C Excellent Temperature Stability Power-Down Mode 32 Lead 5 x 5 mm SMT Package: 25 mm²

0.1 MHz to 500 MHz Clock Generator with Integer N PLL Features: Low current consumption: 1.95 mA typical High phase frequency detector rate: 140 MHz Hardware pin-programmable clock multiplication ratios: 1×/5×/10× Lock detect indicator Power down mode (0.8 μA typical) 8-lead MSOP package: 4.9 mm × 3.0 mm

GaAs MMIC SPDT Switch SMT, DC - 3 GHz Features: Low Insertion Loss: 0.4dB Ultra Small Package: MSOP8 High Input IP3: +50 dBm Positive Control: 0/+3V @ 0.1 uA

Fractional-N PLL with Integrated VCO SMT, 25 - 3000 MHz Features: RF Bandwidth: 25 - 3000 MHz Maximum Phase Detector Rate 100 MHz Ultra Low Phase Noise -110 dBc/Hz in Band Typ. Figure of Merit (FOM) -230 dBc/Hz Integer 40 Lead 6 x 6 mm SMT Package: 36 mm²

32 Gbps, 2:1 Mux with Programmable Output Voltage Features: Supports Data Rates up to 32 Gbps 479 mW Power Consumption −3.3 V or +3.3 V Operation is Available Supports Single-Ended and Differential Operation 24 Lead Ceramic 4 × 4 mm SMT Package: 16 mm2

Clock Generator with Fractional-N PLL & Integrated VCO SMT, 125 - 3000 MHz Features: Frequency Range: 125 - 3000 MHz 78 fs RMS Jitter Generation (Typical) Exceeds G.8251 & GR-253-CORE Jitter Specifications -165 dBc/Hz Phase Noise floor Maximum Phase Detector Rate 100 MHz Figure of Merit (FOM) -227 dBc/Hz 24-Bit Step Size, Resolution 3 Hz Typical Exact Frequency Mode Built-in Digital Self Test 40 Lead 6x6mm SMT Package: 36mm2

High Voltage, Latch-up Proof, 4-Channel Multiplexer Features: Latch-up proof 8 kV HBM ESD rating Low on resistance (<10 Ω) ±9 V to ±22 V dual-supply operation 9 V to 40 V single-supply operation 48 V supply maximum ratings Fully specified at ±15 V, ±20 V, +12 V, and +36 V VSS to VDD analog signal range

High Voltage, Latch-Up Proof, 16-Channel Multiplexer Features: Latch-up proof 3.5 pF off source capacitance 64 pF off drain capacitance 0.35 pC typical charge injection ±0.02 nA on channel leakage Low on resistance: 155 typical ±9 V to ±22 V dual-supply operation 9 V to 40 V single-supply operation VSS to VDD analog signal range Human body model (HBM) ESD rating - 8 kV all other pins

Dual Channel, 16-Bit, 16 MUPS, Multispan, Multi-IO SPI DAC Features: 16-bit resolution 16 MUPS single channel rate in fast mode 11 MUPS single channel rate in precision mode 78 ns small signal settling time to 0.1% accuracy 100 ns large signal settling time to 0.1% accuracy Ultrasmall glitch: <50 pV×s Ultralow latency: 5 ns THD: −105 dB at 1 kHz Highly configurable output voltage span and offset 1.2 V and 1.8 V logic level compatible Single (classic) and dual SPI modes Multiple error detectors, both analog and digital domains 2.5 V internal voltage reference, 10 ppm/°C maximum temperature coefficient Small package: 4 mm × 4 mm LFCSP

Dual Channel, 16-Bit, 33 MUPS, Multispan, Multi-IO SPI DAC Features: 16-bit resolution 33 MUPS single channel rate in fast mode 22 MUPS single channel rate in precision mode 65 ns small signal settling time to 0.1% accuracy 100ns large signal settling time to 0.1% accuracy Ultra small glitch: < 50 pV×s Ultra low latency: 5 ns THD: −105 dB at 1 kHz Highly configurable output voltage span and offset 1.2 V and 1.8 V logic level compatible Single (classic), dual, and quad SPI modes Multiple error detectors, both analog and digital domains 2.5 V internal voltage reference, 10 ppm/°C maximum temperature coefficient 5 mm × 5 mm LFCSP

16-Bit, 2 MSPS/1 MSPS, Precision, Differential SAR ADCs Features: Easy Drive Greatly reduced input kickback Input current reduced to 0.5 μA/MSPS Enhanced acquisition phase, ≥79% of cycle time at 1 MSPS First conversion accurate, no latency or pipeline delay Input span compression for single-supply operation Fast conversion allows low SPI clock rates Input overvoltage clamp protection sinks up to 50 mA SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface High performance Differential analog input range: ±VREF, VREF from 2.4 V to 5.1 V Throughput: 2 MSPS/1 MSPS options INL: ±0.4 LSB maximum Guaranteed 16-bit, no missing codes SNR: 96.2 dB at fIN = 1 kHz, VREF = 5 V THD: −123 dB at fIN = 1 kHz, −99 dB at fIN = 100 kHz SINAD: 88.5 dB at fIN = 1 MHz (see Figure 17 in data sheet) Oversampled dynamic range 99.3 dB for OSR = 2 126 dB for OSR = 1024 Low power Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface 4.9 mW at 1 MSPS (VDD only) 80 μW at 10 kSPS, 16 mW at 2 MSPS (total power) 10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP Pin compatible with AD4003/AD4007/AD4011 family Guaranteed operation: −40°C to +125°C

18-Bit, 2 MSPS/1 MSPS/500 kSPS, Precision, Pseudo Differential, SAR ADCs Features: Easy Drive Greatly reduced input kickback Input current reduced to 0.5 μA/MSPS Enhanced acquisition phase, ≥79% of cycle time at 1 MSPS First conversion accurate, no latency or pipeline delay Input span compression for single-supply operation Fast conversion allows low SPI clock rates Input overvoltage clamp protection sinks up to 50 mA SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface High performance Pseudo differential analog input range 0 V to VREF with VREF from 2.4 V to 5.1 V Throughput: 2 MSPS/1 MSPS/500 kSPS options INL: ±3.2 LSB maximum Guaranteed 18-bit, no missing codes SNR: 95 dB at fIN = 1 kHz at VREF = 5 V THD: −125 dB at fIN = 1 kHz, −108 dB at fIN = 100 kHz SINAD: 84.5 dB at fIN = 1 MHz (see Figure 17 in data sheet) Oversampled dynamic range 98 dB for OSR = 2 125 dB for OSR = 1024 Low power Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface 2.5 mW at 500 kSPS (VDD only) 70 μW at 10 kSPS, 14 mW at 2 MSPS (total power) 10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP Pin compatible with AD4003/AD4007/AD4011 family Guaranteed operation: −40°C to +125°C

Single Supply, 24-Bit, Sigma-Delta ADC with 10 V and 0 mA to 20 mA Inputs Features: Internal or external clock Tested for robustness per: IEC61000-4-2, IEC61000-4-3, IEC61000-4-4, IEC61000-4-5, IEC61000-4-6, CISPR 11 24-bit ADC with integrated analog front end Fast and flexible output rate: 1.25 SPS to 31.25 kSPS Channel scan data rate of 6.21 kSPS per channel (161 μs settling) 16 noise free bits at 1 kSPS per channel 85 dB rejection of 50 Hz and 60 Hz at 20 SPS per channel ±10 V inputs, 4 differential or 8 single-ended Pin absolute maximum rating ±50 V Absolute input pin voltage up to ±20 V ≥1 MΩ impedance ±0.06% accuracy at 25°C 0 mA to 20 mA inputs, 4 single-ended Pin absolute maximum rating ±50 mA Input range from −0.5 mA to +24 mA 60 Ω impedance ±0.08% accuracy at 25°C On-chip 2.5 V reference ±0.12% accuracy at 25°C, ±5 ppm/°C (typical) drift Power supplies AVDD = 3.0 V to 5.5 V IOVDD = 2 V to 5.5 V Total IDD = 3.9 mA Temperature range: −40°C to +105°C 3-wire or 4-wire serial digital interface (Schmitt trigger on SCLK) SPI, QSPI, MICROWIRE, and DSP compatible

Single Supply, 24-Bit, Sigma-Delta ADC with 10 V, 10 M Inputs and Buffered Low Level Inputs Features: 24-bit ADC with integrated analog front end Fast and flexible output rate: 1.25 SPS to 62.5 kSPS Channel scan data rate 12,422 SPS per channel (80 μs settling, sinc5 + sinc1) 20,618 SPS per channel (48 μs settling, sinc3) 85 dB rejection of 50 Hz and 60 Hz at 20 SPS per channel ±10 V inputs, 6 differential or 11 single-ended Pin absolute maximum rating: ±65 V Absolute input pin voltage up to ±20 V ≥10 MΩ impedance Low level direct ADC input ±VREF inputs, 2 differential or 4 single-ended Absolute input pin voltage, AVDD to AVSS True rail-to-rail analog input buffers On-chip 2.5 V reference ±0.12% accuracy at 25°C, ±5 ppm/°C (typical) drift Internal or external clock Power supplies AVDD to AVSS = 4.5 V to 5.5 V IOVDD to DGND = 2 V to 5.5 V Total IDD (AVDD + IOVDD) = 6.15 mA Temperature range: −40°C to +105°C 3-wire or 4-wire serial digital interface (Schmitt trigger on SCLK) SPI, QSPI, MICROWIRE, and DSP compatible

16-Bit, 16-Channel, 500 kSPS/1 MSPS, Easy Drive Multiplexed SAR ADC Features: Easy Drive Reduced analog input and reference drive requirements On-chip reference buffer (WLCSP only) Overvoltage protection up to 5 mA on each analog input Long acquisition phase, ≥71.5% (715 ns/1000 ns) of cycle time at 1 MSPS High performance Sample rate: 500 kSPS (AD4695) or 1 MSPS (AD4696) INL: ±1.0 LSB maximum Guaranteed 16-bit, no missing codes SINAD: 93 dB typical, fIN = 1 kHz Oversampled dynamic range: 111.2 dB, OSR = 64 Small footprint, high channel density 32-lead 5 mm × 5 mm LFCSP 36-ball 2.96 mm × 2.96 mm WLCSP Easy Drive features support system level designs with fewer components Enhanced digital functionality First conversion accurate, no latency or pipeline delay Fast conversion time and dual-/quad-SDO modes allow low SPI clock rates Customizable channel sequencer On-chip oversampling and decimation Threshold detection alerts Offset and gain correction Autonomous conversion (autocycle) mode 1.14 V to 1.98 V logic SPI Low power 8 mW at fS = 1 MSPS and 4 mW at fS = 500 kSPS 4 μW standby power dissipation with the internal LDO disabled Internal LDO enables 3.15 V to 5.5 V, single analog supply operation Wide operating temperature range: −40°C to +125°C

Single Channel, 64-Position, Push-Button, 8% Resistor Tolerance, Nonvolatile Digital Potentiometer Features: Nominal resistor tolerance error: ±8% maximum Wiper current: ±6 mA Rheostat mode temperature coefficient: 35 ppm/°C Low power consumption: 2.5 μA max @ 2.7 V and 125°C Wide bandwidth: 4 MHz (5 kΩ option) Power-on EEPROM refresh time < 50 μs 50-year typical data retention at 125°C 1 million write cycles 2.3 V to 5.5 V supply operation Built-in adaptive debouncer Wide operating temperature: −40°C to +125°C Thin, 2 mm × 2 mm × 0.55 mm, 8-lead LFCSP package