ANALOGUE SWITCH QUAD SPST LFCSP-16; Analogue Switch Type:SPST; No. of Channels:4Channels; On State Resistance Max:475ohm; Supply Voltage Range:12V ± 15V; Analogue Switch Case:LFCSP; No. of Pins:16Pins; Operating Temperature Min:-40°C; Operating Temperature Max:125°C; Packaging:Cut Tape; Product Range:ADG1211 Series; Automotive Qualification Standard:-; MSL:MSL 3 - 168 hours; SVHC:No SVHC (20-Jun-2016)

RS232 TXRX QUAD 230KBPS WSOIC-24; Device Type:RS232 Transceiver; IC Interface Type:RS232; No. of Drivers:4Drivers; No. of Receivers:3Receivers; Supply Voltage Min:4.5V; Supply Voltage Max:5.5V; Driver Case Style:WSOIC; No. of Pins:24Pins; Operating Temperature Min:-40°C; Operating Temperature Max:85°C; Packaging:Cut Tape; Product Range:-; Automotive Qualification Standard:-; MSL:MSL 1 - Unlimited; IC Generic Number:ADM206; SVHC:No SVHC (20-Jun-2016)

Digital to Analog Converters - DAC Single 3V 12bit SPI DAC with reference

Synchronous Rectifier Driver for Forward Converters Features: N-Channel Synchronous Rectifier MOSFET Driver Programmable Timeout Protection Reverse Inductor Current Protection Pulse Transformer Synchronization Wide VCC Supply Range: 4.5V to 11V 15ns Rise/Fall Times at VCC = 5V, CL = 4700pF Undervoltage Lockout Small SO-8 Package

Shunt Voltage Reference IC Fixed 1.235V V -2.83%, +1.22% 5 mA 8-SOIC

Shunt Voltage Reference IC Fixed 1.225V V ±0.08% 10 mA SOT-23-3

Analog to Digital Converters - ADC CMOS CONVERTER IC

SONET/SDH Clock and Data Recovery (CDR), Multiplexer IC 1.25GHz 1 Output 32-LFCSP-WQ (5x5)

12 Channel, 8-Bit TrimDACs with Power Shutdown & Separate VREFL Input Features: Low Cost Replaces 12 Potentiometers Individually Programmable Outputs Power Shutdown < 55 µWatts Including IDD & IREF 3-Wire SPI Compatible Serial Input Midscale Preset, AD8802 Separate VREF Range Settling, AD8804 +3 to +5 Single Supply Operation

14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Analog-to-Digital Converter Features: 1.8 V analog supply operation 1.8 V to 3.3 V output supply SNR = 71.7 dBc (72.7 dBFS) to 70 MHz input SFDR = 85 dBc to 70 MHz input Low power: 395 mW @ 125 MSPS Differential input with 650 MHz bandwidth On-chip voltage reference and sample-and-hold amplifier DNL = ±0.4 LSB Flexible analog input: 1 V p-p to 2 V p-p range Offset binary, Gray code, or twos complement data format Data output clock and clock duty cycle stabilizer Serial port control Built-in selectable digital test pattern generation Programmable clock and data alignment

14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Analog-to-Digital Converter Features: 1.8 V analog supply operation 1.8 V to 3.3 V output supply SNR = 71.7 dBc (72.7 dBFS) to 70 MHz input SFDR = 85 dBc to 70 MHz input Low power: 395 mW @ 125 MSPS Differential input with 650 MHz bandwidth On-chip voltage reference and sample-and-hold amplifier DNL = ±0.4 LSB Flexible analog input: 1 V p-p to 2 V p-p range Offset binary, Gray code, or twos complement data format Data output clock and clock duty cycle stabilizer Serial port control Built-in selectable digital test pattern generation Programmable clock and data alignment

Octal LNA/VGA/AAF/ADC and Crosspoint Switch Features: 8 channels of LNA, VGA, AAF, and ADC Low noise preamplifier (LNA) - See data sheet for additional information Variable gain amplifier (VGA) - See data sheet for additional information Antialiasing filter (AAF) - See data sheet for additional information Analog-to-digital converter (ADC) - See data sheet for additional information Includes an 8 × 8 differential crosspoint switch to support continuous wave (CW) Doppler Low power, 195 mW per channel at 12 bits/40 MSPS (TGC) See data sheet for additional features

8-Bit, 50 MSPS/80 MSPS/100 MSPS ADC Features: Low Power: 90 mW at 100 MSPS On-Chip Reference and Track/Hold 475 MHz Analog Bandwidth 46.5 dB SNR at 100 MSPS with 41 MHz input 1 Vp-p Analog Input Range Single +3.0 V Supply Operation (2.7 -3.6 V) Power Down Mode: 4.2 mW

Ethernet/Gigabit Ethernet Clock Generator Features: Redundant input reference clock capability Reference monitoring function Fully integrated VCO/PLL core Jitter (rms) 0.234 ps rms jitter (10 kHz to 10 MHz) at 156.25 MHz 0.243 ps rms jitter (12 kHz to 20 MHz) at 156.25 MHz Input frequency: 19.44 MHz or 25 MHz Preset frequency translations Using a 19.44 MHz input reference 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz Using a 25 MHz input reference 25 MHz, 33.33 MHz, 50 MHz, 66.67 MHz, 80 MHz, 100 MHz, 125 MHz, 133.3 MHz, 156.25 MHz, 160 MHz, 312.5 MHz Output drive formats: HSTL, LVDS, HCSL, and 1.8 V and 3.3 V CMOS Integrated loop filter (requires a single external capacitor) 2 copies of reference clock output Device configuration via strapping pins (PPRx) Space-saving 7 mm × 7 mm 48-lead LFCSP 3.3 V operation

16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) Features: 1.8 V analog supply operation 1.8 V CMOS or LVDS output supply SNR 82 dBFS at 30 MHz input and 105 MSPS data rate 83 dBFS at 9.7 MHz input and 25 MSPS data rate SFDR 90 dBc at 30 MHz input and 105 MSPS data rate 95 dBc at 9.7 MHz input and 25 MSPS data rate Low power 328 mW per channel at 105 MSPS 119 mW per channel at 25 MSPS Integer 1-to-8 input clock divider See data sheet for additional featuresAD9650-EP supports defense and aerospace applications (AQEC standard) Download AD9650-EP data sheet (pdf)

10-Bit, 100 MSPS+ TxDAC D/A Converter Features: Member of Pin-Compatible TxDAC Product Family 125 MSPS Update Rate 10-Bit Resolution Excellent Spurious Free Dynamic Range Performance SFDR to Nyquist @ 40 MHz Output: 52 dBc Differential Current Outputs: 2 ma to 20 mA Edge-Triggered Latches See datasheet for additional features

16-Bit 160 MSPS 2x/4x/8x Interpolating Dual TxDAC+ D/A Converter Features: 16-bit resolution, 160 MSPS/400 MSPS input/output data rate Selectable 2×/4×/8× interpolating filter Programmable channel gain and offset adjustment fS/4, fS/8 digital quadrature modulation capability Fully compatible SPI® port Direct IF transmission mode for 70 MHz + IFs Enables image rejection architecture See datasheet for additional features

Dual, 12-Bit, 1 GSPS, Digital-to-Analog Converter Features: Low power: 1.0 W @ 1 GSPS, 600 mW @ 500 MSPS, full operating conditions Single carrier W-CDMA ACLR = 80 dBc @ 80 MHz IF Analog output: adjustable 8.7 mA to 31.7 mA, RL = 25 Ω to 50 Ω Novel 2×, 4×, and 8× interpolator/coarse complex modulator allows carrier placement anywhere in DAC bandwidth Auxiliary DACs allow control of external VGA and offset control Multiple chip synchronization interface High performance, low noise PLL clock multiplier Digital inverse sinc filter 100-lead, exposed paddle TQFP

AD9847 - AFE Video 1ADC 10bit 3.3V/5V 48-Pin LFCSP EP

10-/12-Bit Mixed Signal Front-End (MxFE) Processor for Broadband Communications Features: Dual 10-/12-Bit, 64 MSPS Sampling A/D Converter with Independent Reference, Input Buffers, Programmable Gain Amplifiers (PGA), Decimation Filters and a Digital Hilbert Block Dual 12-/14-bit, 128 MSPS D/A Converter with Digital Hilbert and Interpolation Filters, Digital I/Q or Real-Signal Up-Converters, By passable Digital Up-Converters A Versatile Mixed Signal Front-End Processor with Dual Receive and Dual Transmit Channels Internal Clock Distribution Block including a Phase-Locked Loop and Timing Generation circuitry Programmable Output Clocks, SPI Port, Programmable Sigma Delta Outputs, Auxiliary DAC outputs, Auxiliary ADC inputs