Aerospace Low Input Current Operational Amplifier Features:Low Offset Current: 200pA Max Low Bias Current: 2nA Max Low Power Consumption Wide Supply Range: 3V to 20V High Power-Supply Rejection Ratio Low Offset Voltage Drift: 5V/C Max High Common-Mode Input Range High Common-Mode Rejection Ratio: 96dB Min

Dual Channel, 12-Bit, 40 MSPS MCM A/D Converter with DC-Coupled Analog Input Signal Conditioning (AD9042 Core ADC) Features: 2 Matched ADCs with Input Signal Conditioning Selectable Bipolar Input Voltage Range (±0.5 V, ±1.0 V, ±2.0 V) Full MIL-STD-883B Compliant 80 dB Spurious-Free Dynamic Range Trimmed Channel-Channel Matching

3.0V Micropower, Precisions Series Mode Voltage References Features: Series reference (2.5 V, 3 V, 4.096 V, 5 V) Low quiescent current: 70 µA maximum Current output capability: ±5 mA Wide supply range: VIN = VOUT + 200 mV to 12 V Wideband noise (10 Hz to 10 kHz): 50 µV rms Specified temperature range: −40°C to +125°C Compact, surface-mount SOT-23 package Qualified for automotive applications

8-Channel DAC with PLL and Differential Outputs, 192 kHz, 24 Bits Features:PLL generated or direct master clockLow EMI designDAC with 110 dB dynamic range and SNR96 dB THD + N3.3 V single supplyTolerance for 5 V logic inputsSupports 24 bits and 8 kHz to 192 kHz sample ratesDifferential DAC outputLog volume control with autoramp functionSPI controllable for flexibilitySoftware-controllable clickless muteSee data sheet for additional features

Enhanced Automotive Audio Bus (A2B) Transceiver supporting Slave operation Features: High bandwidth (50Mbps) digital bus support for up to 32 upstream and downstream audio channels Data, control, plus power on a single wire pair provides system cost reduction using low-cost unshielded, twisted pair cable Single-master, multiple-slave, line topology supports daisy chaining with zero processor intervention Phantom power capability eliminates the need for local power supplies Embedded diagnostics provide easy system level fault detection & correction Fully configurable via SigmaStudio™ graphical design environment promotes Fast time to market

Enhanced Automotive Audio Bus (A2B) Transceiver supporting both Master and Slave operation Features: High bandwidth (50Mbps) digital bus support for up to 32 upstream and downstream audio channels Data, control, plus power on a single wire pair provides system cost reduction using low-cost unshielded, twisted pair cable Single-master, multiple-slave, line topology supports daisy chaining with zero processor intervention Phantom power capability eliminates the need for local power supplies Embedded diagnostics provide easy system level fault detection & correction Fully configurable via SigmaStudio™ graphical design environment promotes Fast time to market

A2B Last-in-Line Subordinate 4xPDM XCVR Features:A2B BUS FEATURES Line topology Single main node, multiple subordinate nodes Up to 15 m between nodes and up to 40 m overall cable length Communication over distance Synchronous data Multichannel I2S/TDM to I2S/TDM Synchronous clock, phase aligned in all nodes Low latency node to node communication Control and status information I2C to I2C GPIO and interrupt Bus power or local power subordinate nodes Configurable with SigmaStudio/SigmaStudio+ graphical software tool AEC-Q100 qualified for automotive applicationsA2B TRANSCEIVER FEATURES Configurable A2B bus main node or subordinate node Programmable via I2C interface 8-bit to 32-bit multichannel I2S/TDM interface Programmable I2S/TDM data rate Up to 32 upstream and 32 downstream channels PDM interface Programmable PDM clock rate Up to 4 high dynamic range microphone inputs Simultaneous reception of I2S data with up to 4 PDM microphones Unique ID register for each transceiver Crossover or straight-through cabling Programmable settings to optimize EMC performance

A2B Main 4xPDM XCVR wI2S/TDM Features:A2B BUS FEATURES Line topology Single main node, multiple subordinate nodes Up to 15 m between nodes and up to 40 m overall cable length Communication over distance Synchronous data Multichannel I2S/TDM to I2S/TDM Synchronous clock, phase aligned in all nodes Low latency node to node communication Control and status information I2C to I2C GPIO and interrupt Bus power or local power subordinate nodes Configurable with SigmaStudio/SigmaStudio+ graphical software tool AEC-Q100 qualified for automotive applicationsA2B TRANSCEIVER FEATURES Configurable A2B bus main node or subordinate node Programmable via I2C interface 8-bit to 32-bit multichannel I2S/TDM interface Programmable I2S/TDM data rate Up to 32 upstream and 32 downstream channels PDM interface Programmable PDM clock rate Up to 4 high dynamic range microphone inputs Simultaneous reception of I2S data with up to 4 PDM microphones Unique ID register for each transceiver Crossover or straight-through cabling Programmable settings to optimize EMC performance

Single Channel, 16-Bit, 16 MUPS, Multispan, Multi-IO SPI DAC Features: 16-bit resolution 16 MUPS single channel rate in fast mode 11 MUPS single channel rate in precision mode 78 ns small signal settling time to 0.1% accuracy 100 ns large signal settling time to 0.1% accuracy Ultrasmall glitch: <50 pV×s Ultralow latency: 5 ns THD: −105 dB at 1 kHz Highly configurable output voltage span and offset 1.2 V and 1.8 V logic level compatible Single (classic) and dual SPI modes Multiple error detectors, both analog and digital domains 2.5 V internal voltage reference, 10 ppm/°C maximum temperature coefficient Small package: 4 mm × 4 mm LFCSP

Quad 12-Bit Microprocessor-Compatible D/A Converter Features:Four Complete 12-Bit DACs in One IC PackageLinearity Error 1/2LSF Tmin - Tmax(AD390K, T)Factory-Trimmed Gain and OffsetBuffered Voltage OutputMonotonicity Guaranteed Over Full Temperature RangeDouble-Buffered Data LatchesIncludes Reference and BufferFast Setting: 8s max to 1/2LSB

18-Bit, 2 MSPS/1 MSPS/500 kSPS, Precision, Pseudo Differential, SAR ADCs Features: Easy Drive Greatly reduced input kickback Input current reduced to 0.5 μA/MSPS Enhanced acquisition phase, ≥79% of cycle time at 1 MSPS First conversion accurate, no latency or pipeline delay Input span compression for single-supply operation Fast conversion allows low SPI clock rates Input overvoltage clamp protection sinks up to 50 mA SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface High performance Pseudo differential analog input range 0 V to VREF with VREF from 2.4 V to 5.1 V Throughput: 2 MSPS/1 MSPS/500 kSPS options INL: ±3.2 LSB maximum Guaranteed 18-bit, no missing codes SNR: 95 dB at fIN = 1 kHz at VREF = 5 V THD: −125 dB at fIN = 1 kHz, −108 dB at fIN = 100 kHz SINAD: 84.5 dB at fIN = 1 MHz (see Figure 17 in data sheet) Oversampled dynamic range 98 dB for OSR = 2 125 dB for OSR = 1024 Low power Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface 2.5 mW at 500 kSPS (VDD only) 70 μW at 10 kSPS, 14 mW at 2 MSPS (total power) 10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP Pin compatible with AD4003/AD4007/AD4011 family Guaranteed operation: −40°C to +125°C

20-Bit, 1.8 MSPS/1 MSPS/500 kSPS, Easy Drive, Differential SAR ADCs Features: Easy Drive Greatly reduced input kickback Input current reduced to 0.5 μA/MSPS Enhanced acquisition phase, ≥77% of cycle time at 1 MSPS First conversion accurate, no latency or pipeline delay Input span compression for single-supply operation Fast conversion allows low SPI clock rates Input overvoltage clamp protection sinks up to 50 mA SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface High performance Differential analog input range: ±VREF, VREF from 2.4 V to 5.1 V Throughput: 1.8 MSPS/1 MSPS/500 kSPS options INL: ±3.1 ppm maximum Guaranteed 20-bit, no missing codes SNR: 100.5 dB at fIN = 1 kHz, VREF = 5 V THD: −123 dB at fIN = 1 kHz, −100 dB at fIN = 100 kHz SINAD: 89 dB at fIN = 900 kHz (see Figure 17 in the data sheet) Oversampled dynamic range 104 dB for OSR = 2 131 dB for OSR = 1024 Low power Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface 2.7 mW at 500 kSPS (VDD only) 83 μW at 10 kSPS, 15 mW at 1.8 MSPS (total power) 10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP Pin compatible with AD4003/AD4007/AD4011 family Guaranteed operation: −40°C to +125°C

20-Bit, 1.8 MSPS/1 MSPS/500 kSPS, Easy Drive, Differential SAR ADCs Features: Easy Drive Greatly reduced input kickback Input current reduced to 0.5 μA/MSPS Enhanced acquisition phase, ≥77% of cycle time at 1 MSPS First conversion accurate, no latency or pipeline delay Input span compression for single-supply operation Fast conversion allows low SPI clock rates Input overvoltage clamp protection sinks up to 50 mA SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface High performance Differential analog input range: ±VREF, VREF from 2.4 V to 5.1 V Throughput: 1.8 MSPS/1 MSPS/500 kSPS options INL: ±3.1 ppm maximum Guaranteed 20-bit, no missing codes SNR: 100.5 dB at fIN = 1 kHz, VREF = 5 V THD: −123 dB at fIN = 1 kHz, −100 dB at fIN = 100 kHz SINAD: 89 dB at fIN = 900 kHz (see Figure 17 in the data sheet) Oversampled dynamic range 104 dB for OSR = 2 131 dB for OSR = 1024 Low power Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface 2.7 mW at 500 kSPS (VDD only) 83 μW at 10 kSPS, 15 mW at 1.8 MSPS (total power) 10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP Pin compatible with AD4003/AD4007/AD4011 family Guaranteed operation: −40°C to +125°C

20-Bit, 1.8 MSPS/1 MSPS/500 kSPS, Easy Drive, Differential SAR ADCs Features: Easy Drive Greatly reduced input kickback Input current reduced to 0.5 μA/MSPS Enhanced acquisition phase, ≥77% of cycle time at 1 MSPS First conversion accurate, no latency or pipeline delay Input span compression for single-supply operation Fast conversion allows low SPI clock rates Input overvoltage clamp protection sinks up to 50 mA SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface High performance Differential analog input range: ±VREF, VREF from 2.4 V to 5.1 V Throughput: 1.8 MSPS/1 MSPS/500 kSPS options INL: ±3.1 ppm maximum Guaranteed 20-bit, no missing codes SNR: 100.5 dB at fIN = 1 kHz, VREF = 5 V THD: −123 dB at fIN = 1 kHz, −100 dB at fIN = 100 kHz SINAD: 89 dB at fIN = 900 kHz (see Figure 17 in the data sheet) Oversampled dynamic range 104 dB for OSR = 2 131 dB for OSR = 1024 Low power Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface 2.7 mW at 500 kSPS (VDD only) 83 μW at 10 kSPS, 15 mW at 1.8 MSPS (total power) 10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP Pin compatible with AD4003/AD4007/AD4011 family Guaranteed operation: −40°C to +125°C

Single Supply, 24-Bit, Sigma-Delta ADC with 10 V, 10 M Inputs and Buffered Low Level Inputs Features: 24-bit ADC with integrated analog front end Fast and flexible output rate: 1.25 SPS to 62.5 kSPS Channel scan data rate 12,422 SPS per channel (80 μs settling, sinc5 + sinc1) 20,618 SPS per channel (48 μs settling, sinc3) 85 dB rejection of 50 Hz and 60 Hz at 20 SPS per channel ±10 V inputs, 6 differential or 11 single-ended Pin absolute maximum rating: ±65 V Absolute input pin voltage up to ±20 V ≥10 MΩ impedance Low level direct ADC input ±VREF inputs, 2 differential or 4 single-ended Absolute input pin voltage, AVDD to AVSS True rail-to-rail analog input buffers On-chip 2.5 V reference ±0.12% accuracy at 25°C, ±5 ppm/°C (typical) drift Internal or external clock Power supplies AVDD to AVSS = 4.5 V to 5.5 V IOVDD to DGND = 2 V to 5.5 V Total IDD (AVDD + IOVDD) = 6.15 mA Temperature range: −40°C to +105°C 3-wire or 4-wire serial digital interface (Schmitt trigger on SCLK) SPI, QSPI, MICROWIRE, and DSP compatible

Bidirectional, Zero-Drift, Current Sense Amplifier Features: Typical 0.1 μV/°C offset drift Maximum ±200 μV voltage offset over full temperature range 2.7 V to 5.5 V power supply operating range Electromagnetic interference (EMI) filters included High common-mode input voltage range −2 V to +70 V, continuous operation −3 V to +80 V, continuous survival Minimum DC common-mode rejection ratio (CMRR): 90 dB Initial gain = 20 V/V Wide operating temperature range AD8418AWB and AD8418AB: −40°C to +125°C AD8418AWH: −40°C to +150°C Bidirectional operation Available in 8-lead SOIC_N, 8-lead MSOP, and FMEA tolerant 10-lead MSOP pinout AEC-Q100 qualified for automotive applications

16-Bit, 2 MSPS, Dual Channel SAR ADC Features: High performance Throughput: 2 MSPS per channel maximum INL: ±3 ppm maximum from −40°C to +125°C SNR: 97.4 dB typical THD: −127 dB typical NSD: −157.4 dBFS/Hz typical Low power 15 mW per channel at 2 MSPS 1.5 mW per channel at 10 kSPS Easy Drive features reduce system complexity Low 0.6 μA input current for dc inputs Wide common-mode input range: −(1/128) × VREF to +(129/128) × VREF Flexible external reference voltage range: 4.096 V to 5 V Accurate integrated reference buffer with 2 μF bypass capacitor Programmable block averaging filter with up to 216 decimation Extended sample resolution to 30 bits Over range and synchronization bits Flexi-SPI digital interface 1, 2, or 4 SDO lanes per channel allows slower SCK Echo clock mode simplifies use of digital isolator Compatible with 1.2 V to 1.8 V logic 7 mm × 7 mm 64-Ball CSP_BGA package with internal supply and reference capacitors to help reduce system footprint

Differential Inputs, 1 MSPS, Dual Simultaneous Sampling SAR ADCs Features: 16-bit ADC family Dual simultaneous sampling Fully differential analog inputs Throughput conversion rate 1 MSPS for AD4680 500 kSPS for AD4681 SNR (typical) 92.5 dB, VREF = 3.3 V external 100 dB with 8× OSR, RES = 1 On-chip oversampling function Resolution boost function INL (maximum) 1.5 LSBs 2.5 V internal reference at 10 ppm/°C High speed serial interface −40°C to +125°C operation 3 mm × 3 mm, 16-lead LFCSP Wide common-mode range Alert function

Pseudo Differential Input, 1 MSPS/500 kSPS, Dual, Simultaneous Sampling, 16-Bit, SAR ADCs Features:Dual 16-bit ADC familyDual simultaneous samplingPseudo differential analog inputsThroughput conversion rate 1 MSPS for the AD4682 500 kSPS for the AD4683 SNR (typical) 87.5 dB, VREF = 3.3 V external 93.4 dB with RES = 1 and OSR = ×8 On-chip oversampling functionAlert functionResolution boost functionINL error (maximum): 2.5 LSBs2.5 V internal referenceHigh speed serial interface40C to +125C operation3 mm × 3 mm, 16-lead LFCSP

16-Bit, 16-Channel, 500 kSPS/1 MSPS, Easy Drive Multiplexed SAR ADC Features: Easy Drive Reduced analog input and reference drive requirements On-chip reference buffer (WLCSP only) Overvoltage protection up to 5 mA on each analog input Long acquisition phase, ≥71.5% (715 ns/1000 ns) of cycle time at 1 MSPS High performance Sample rate: 500 kSPS (AD4695) or 1 MSPS (AD4696) INL: ±1.0 LSB maximum Guaranteed 16-bit, no missing codes SINAD: 93 dB typical, fIN = 1 kHz Oversampled dynamic range: 111.2 dB, OSR = 64 Small footprint, high channel density 32-lead 5 mm × 5 mm LFCSP 36-ball 2.96 mm × 2.96 mm WLCSP Easy Drive features support system level designs with fewer components Enhanced digital functionality First conversion accurate, no latency or pipeline delay Fast conversion time and dual-/quad-SDO modes allow low SPI clock rates Customizable channel sequencer On-chip oversampling and decimation Threshold detection alerts Offset and gain correction Autonomous conversion (autocycle) mode 1.14 V to 1.98 V logic SPI Low power 8 mW at fS = 1 MSPS and 4 mW at fS = 500 kSPS 4 μW standby power dissipation with the internal LDO disabled Internal LDO enables 3.15 V to 5.5 V, single analog supply operation Wide operating temperature range: −40°C to +125°C