LTC7138 - High Efficiency, 140V 400mA Step-Down Regulator

High Power PD with Synchronous No-Opto Flyback Controller Features: Robust 35W PD Front End IEEE 802.3af Compliant Rugged 750mA Power MOSFET with Precision Dual Level Current Limit High Performance Synchronous Flyback Controller IEEE Isolation Obtained Without an Opto-Isolator Adjustable Frequency from 50kHz to 250kHz Tight Multi-Output Regulation with Load Compensation On-board 25k Signature Resistor Programmable Classification Current to 75mA Complete Thermal and Over-Current Protection Available in Compact 32-Pin 7mm × 4mm DFN Package

1826-1349 SELECTED SPN IC

385 MHz BW IF Diversity Receiver Features: JESD204B (Subclass 1) coded serial digital outputs In band SFDR = 83 dBFS at 340 MHz (750 MSPS) In band SNR = 66.7 dBFS at 340 MHz (750 MSPS) 1.4 W total power per channel at 750 MSPS (default settings) Noise density = −153 dBFS/Hz at 750 MSPS 1.25 V, 2.5 V, and 3.3 V dc supply operation Flexible input range AD6674-750 and AD6674-1000 1.46 V p-p to 1.94 V p-p (1.70 V p-p nominal) AD6674-500 1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal) 95 dB channel isolation/crosstalk Amplitude detect bits for efficient automatic gain control (AGC) implementation Noise shaping requantizer (NSR) option for main receiver function Variable dynamic range (VDR) option for digital predistortion (DPD) function 2 integrated wideband digital processors per channel 12-bit numerically controlled oscillator (NCO), up to 4 cascaded half-band filters Differential clock inputs Integer clock divide by 1, 2, 4, or 8 Energy saving power-down modes Flexible JESD204B lane configurations Small signal dither

385 MHz BW IF Diversity Receiver Features: JESD204B (Subclass 1) coded serial digital outputs In band SFDR = 83 dBFS at 340 MHz (750 MSPS) In band SNR = 66.7 dBFS at 340 MHz (750 MSPS) 1.4 W total power per channel at 750 MSPS (default settings) Noise density = −153 dBFS/Hz at 750 MSPS 1.25 V, 2.5 V, and 3.3 V dc supply operation Flexible input range AD6674-750 and AD6674-1000 1.46 V p-p to 1.94 V p-p (1.70 V p-p nominal) AD6674-500 1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal) 95 dB channel isolation/crosstalk Amplitude detect bits for efficient automatic gain control (AGC) implementation Noise shaping requantizer (NSR) option for main receiver function Variable dynamic range (VDR) option for digital predistortion (DPD) function 2 integrated wideband digital processors per channel 12-bit numerically controlled oscillator (NCO), up to 4 cascaded half-band filters Differential clock inputs Integer clock divide by 1, 2, 4, or 8 Energy saving power-down modes Flexible JESD204B lane configurations Small signal dither

2-Channel, 1 MSPS, Ultralow Power, 12-Bit ADC in 16-Lead TSSOP Features: Ultralow system power Flexible power/throughput rate management High performance 1 MSPS throughput with no latency/pipeline delay SNR: 70 dB typical at 10 kHz input frequency THD: −80 dB typical at 10 kHz input frequency INL: ±0.7 LSB typical, ±1.0 LSB maximum Small system footprint On-chip accurate 2.5 V reference, 5 ppm/°C typical drift MUXOUT/ADCIN to allow single buffer amplifier Daisy-chain mode 16-lead, 20-lead, and 24-lead 4 mm × 4 mm LFCSP packages See data sheet for additional features.

10-Bit, 20 MSPS, 80 mW CMOS A/D Converter Features: CMOS 10-Bit, 20 MSPS Sampling A/D Converter Pin-Compatible with AD876 Power Dissipation: 80 mW (3 V Supply) Operation Between 2.7 V and 5.5 V Supply Differential Nonlinearity: 0.5 LSB Power-Down (Sleep) Mode Three-State Outputs See datasheet for additional features

10-Bit, 200 MSPS/250 MSPS/300 MSPS, 1.8 V Analog-to-Digital Converter Features: SNR = 60.1 dBFS @ fIN up to 70 MHz @  300 MSPS ENOB of 9.7 @ fIN up to 70 MHz @ 300 MSPS (−1.0 dBFS) SFDR = −80 dBc @ fIN up to 70 MHz @ 300 MSPS (−1.0 dBFS) Excellent linearity  DNL = ±0.1 LSB typical  INL = ±0.2 LSB typical LVDS at 300 MSPS (ANSI-644 levels) 700 MHz full power analog bandwidth On-chip reference, no external decoupling required Integrated input buffer and track-and-hold Low power dissipation  437 mW @ 300 MSPS—LVDS SDR mode 410 mW @ 300 MSPS—LVDS DDR mode Programmable input voltage range  1.0 V to 1.5 V, 1.25 V nominal 1.8 V analog and digital supply operation Selectable output data format (offset binary, twos complement, Gray code)

10-Bit, 65/80/105 MSPS Dual A/D Converter Features: Integrated Dual 10-Bit A/D Converters Low Power: 300 mW at 105 MSPS 234 mW at 80 MSPS 216 mW at 65 MSPS Single 3 V Supply Operation (2.7 V to 3.3 V) SNR = 57.6 dBc (to Nyquist, AD9216-105) SFDR = 74 dBc (to Nyquist, AD9216-105) Low Power: 280 mW at 105 MSPS Differential Input with 500 MHz 3 dB Bandwidth Exceptional Cross Talk Immunity > 75 dB Flexible Analog Input: 1 V p-p to 2 V p-p Range Offset Binary or Twos Complement Data Format Clock Duty Cycle Stabilizer Pin-compatible with the AD9238 and AD9248

Buck, SEPIC Switching Regulator IC Positive Adjustable 2.42V 1 Output 4.5A (Switch) TO-263-8, D²Pak (7 Leads + Tab), TO-263CA

12-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter Features: SNR = 64.8 dBFS @ fIN up to 70 MHz @ 250 MSPS ENOB of 10.5 @ fIN up to 70 MHz @ 250 MSPS (−1.0 dBFS) SFDR = 80 dBc @ fIN up to 70 MHz @ 250 MSPS (−1.0 dBFS) Excellent Linearity DNL = ±0.3 LSB typical INL = ±0.7 LSB typical CMOS outputs Single data port at up to 250 MHz Interleaved dual port @ 1/2 sample rate up to 125 MHz 700 MHz full power analog bandwidth On-chip reference, no external decoupling required Integrated input buffer and track-and-hold Low power dissipation 272 mW @ 170 MSPS 364 mW @ 250 MSPS Programmable input voltage range 1.0 V to 1.5 V, 1.25 V nominal 1.8 V analog and digital supply operation Selectable output data format (offset binary, twos complement, Gray code)

10-Bit, Complete, 40 MSPS, dual Transmit D/A Converter Features: Complete 10-Bit, 40 MSPS Dual Transmit DAC Excellent Gain and Offset Matching Differential Nonlinearity Error: 0.5 LSB Effective Number of Bits: 9.5 Signal-to-Noise and Distortion Ratio: 59 dB Spurious-Free Dynamic Range: 71 dB 2x Interpolation Filters See datasheet for additional features

Dual 14-Bit, 1 GSPS, Digital-to-Analog Converter Features: Low power: 1.0 W @ 1 GSPS, 600 mW @ 500 MSPS, full operating conditions SFDR = 78 dBc to fOUT = 100 MHz Single carrier WCDMA ACLR = 79 dBc @ 80 MHz IF Novel 2×, 4×, and 8× interpolator/coarse complex modulator allows carrier placement anywhere in DAC bandwidth Analog output: adjustable 8.7 mA to 31.7 mA, RL = 25 Ω to 50 Ω Auxiliary DACs allow control of external VGA and offset control Multiple chip synchronization interface High performance, low noise PLL clock multiplier Digital inverse sinc filter 100-lead, exposed paddle TQFP package

Broadband Modem Mixed-Signal Front End Features: Low cost, 3.3 V CMOS MxFE® for broadband modems 10-bit digital-to-analog converter (DAC) 2×/4× interpolation filter 250 MSPS DAC update rate 10-bit, 75 MSPS ADC Low noise RxPGA Dual channel muxed input 6 dB input overload attenuator −12 dB to +48 dB (without attenuator) Third-order programmable low-pass filter Flexible digital datapath interface Half-duplex and full-duplex operation Programmable delay Tx driver disable signal Various power-down/reduction modes Internal clock multiplier (PLL) 2 auxiliary programmable clock outputs 64-lead LFCSP

High Speed , 8-Channel, 8-Bit CMOS ADC Features: 4 or 8 Analog Input Channels Built-In Track-and-Hold Function 10 kHz Signal Handling on Each Channel Fast Microprocessor Interface Single 5 V Supply Low Power: 50 mW Fast Conversion Rate: 2.5 µs/Channel Tight Error Specification: 1/2 LSB

Complete 12-Bit CMOS Multiplying DAC Features: 12-Bit CMOS MDAC with Output Amplifier 4-Quadrant Multiplication Low Power LC2MOS Guaranteed Monotonic (Tmin to Tmax) Space-Saving 0.3' DIPS and 24- or 28- Terminal Surface Mount Packages Application Resistors On Chip for Gain Ranging, etc.

Complete 12-Bit CMOS Multiplying DAC Features: 12-Bit CMOS MDAC with Output Amplifier 4-Quadrant Multiplication Low Power LC2MOS Guaranteed Monotonic (Tmin to Tmax) Space-Saving 0.3' DIPS and 24- or 28- Terminal Surface Mount Packages Application Resistors On Chip for Gain Ranging, etc.

LC2MOS Complete, Dual 12-Bit MDAC, Parallel Loading Structure Features: Two 12-Bit MDACs with Output Amplifiers Space-Saving 0.3', 24-Lead DIP an 24-Terminal SOIC Package 4-Quadrant Multiplication Parallel Loading Structure: AD7847 (8+4) Loading Structure: AD7837

Simultaneous Sampling Dual 250 kSPS 12-Bit ADC Features: Two Fast 12-Bit ADCs Four Input Channels Simultaneous Sampling & Conversion 4 µs Throughput Time Single Supply Operation High Speed Parallel Interface Low Power, 60 mW typ Selection of Input Ranges: ±10 V for AD7862-10 ±2.5 V for AD7862-3 0 V to 2.5 V for AD7862-2 Power Saving Mode, 50 µW typ Overvoltage Protection on Analog Inputs 14-Bit Pin Compatible Upgrade (AD7863)

Complete 12-Bit, 100 kHz, Sampling ADC (AD7870/AD7870A) Features: Complete Monolithic 12-Bit ADC with: 2 µs Track/Hold Amplifier 8 µs A/D Converter On-Chip Reference Laser-Trimmed Clock Parallel, Byte and Serial Digital Interface 57 ns Data Access Time 72 dB SNR at 10 kHz Input Frequency (AD7870, AD7875) Low Power: –60 mW typ Variety of Input Ranges: ±3 V for AD7870 0 V to +5 V for AD7875 ±10 V for AD7876