The ADAQ4003 is a ?Module? precision data acquisition (DAQ), signal chain solution that reduces the development cycle of a precision measurement system by transferring the signal chain design challenge of component selection, optimization, and layout from the designer to the device.Using system-in-package (SIP) technology, the ADAQ4003 reduces end system component count by combining multiple common signal processing and conditioning blocks into a single device. These blocks include a high resolution 18-bit, 2 MSPS successive approximation register (SAR), analog-to-digital converter (ADC), a low noise, fully differential ADC driver amplifier (FDA), and a stable reference buffer.Using Analog Devices, Inc., iPassives? technology, the ADAQ4003 also incorporates crucial passive components with superior matching and drift characteristics to minimize temperature dependent error sources and to offer optimized performance (see Figure 1 in the data sheet). Housing this signal chain solution in a small, 7 mm ? 7 mm, 0.80 mm pitch, 49-ball CSP_BGA enables compact form factor designs without sacrificing performance and simplifies end system bill of materials management. This level of system integration makes the ADAQ4003 much less sensitive to printed circuit board (PCB) layout while still providing flexibility to adapt to a wide range of signal levels.The serial peripheral interface (SPI)-compatible, serial user interface is compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic, using a separate VIO supply. Specified operation of ADAQ4003 is from ?40?C to +125?C.APPLICATIONS Automatic test equipment Machine automation Process controls Medical instrumentation Digital control loops

The ADAQ8088 is a dual-channel analog system in package (SIP) that integrates three common signal processing and conditioning blocks to support a variety of demodulator applications and data acquisition applications. The device integrates all active and passive components to form a complete signal chain between the output of an I/Q demodulator and the input to an analog-to-digital converter (ADC). The device also forms the complete signal chain between a transducer output and the input to an ADC in baseband data acquisition systems. No external components are required for proper functionality. Each channel contains a preamplifier, followed by an 8-pole, low-pass filter with a 36 MHz, 3 dB frequency and a differential ADC driver optimized to drive 12-bit to 14-bit pipeline ADCs with speeds up to 150 MSPS. Encapsulated in a 6 mm ? 12 mm CSP_BGA package, the ADAQ8088 minimizes space requirements in high density multichannel systems. The ADAQ8088 operating temperature range is from ?40?C to +85?C. APPLICATIONS IF broadband demodulators Medical imaging (CW ultrasound beam forming) Phased array systems Radar Adaptive antennas Communications receivers Radio Links Wireless local loop RF instrumentation Satellite modems Baseband data acquisition system Multichannel digitizer instruments Ultrasonic non-destructive test

The ADATE318 is a complete, single-chip ATE solution that performs the pin electronics functions of driver, comparator, and active load (DCL), four quadrant, per pin, parametric measurement unit (PPMU). It has VHH drive capability per chip to support flash memory testing applications and integrated 16-bit DACs with an on-chip calibration engine to provide all necessary dc levels for operation of the part.The driver features three active states: data high, data low, and terminate mode, as well as a high impedance inhibit state. The inhibit state, in conjunction with the integrated dynamic clamps, facilitates the implementation of a high speed active termination. The output voltage capability is ?1.5 V to +6.5 V to accommodate a wide range of ATE and instrumentation applications.The ADATE318 can be used as a dual, single-ended drive/ receive channel or as a single differential drive/receive channel. Each channel of the ADATE318 features a high speed window comparator as well as a programmable threshold differential comparator for differential ATE applications. A four quadrant PPMU is also provided per channel.All dc levels for DCL and PPMU functions are generated by 24 on-chip 16-bit DACs. To facilitate accurate levels programming, the ADATE318 contains an integrated calibration function to correct gain and offset errors for each functional block. Correction coefficients can be stored on chip, and any values written to the DACs are automatically adjusted using the appropriate correction factors.The ADATE318 uses a serial programmable interface (SPI) bus to program all functional blocks, DACs, and on-chip calibration constants. It also has an on-chip temperature sensor and over/undervoltage fault clamps for monitoring and reporting the device temperature and any output pin or PPMU voltage faults that may occur during operation.Applications Automatic test equipment Semiconductor test systems Board test systems Instrumentation and characterization equipment

The ADATE334 is a complete dual-channel automatic test equipment (ATE) solution that performs the pin electronics functions of a driver, comparator, and active load (DCL), and a four-quadrant per pin parametric measurement unit (PPMU). Dedicated, 16-bit DACs with on-chip calibration registers provide all necessary dc levels for device operation.The high voltage driver features three active states: high mode, low mode, and terminate mode, as well as a high impedance inhibit state. The inhibit state, in conjunction with the integrated dynamic clamps, facilitates significant attenuation of transmission line reflections when the driver is not actively terminating the line. The open-circuit drive capability is ?1.5 V to +7.0 V to accommodate a wide range of ATE and instrumentation applications.The low voltage driver, working in conjunction with the high voltage driver, can provide 25 mV p-p to 600 mV p-p signals at up to 4.6 Gbps in a 50 ? environment.The ADATE334 can be used either as a dual, single-ended pin electronics channel or as a single differential channel. In addition to per-channel, high speed window comparators, the ADATE334 provides a programmable threshold differential comparator for differential ATE applications and a zero-crossing comparator.All dc levels for DCL and PPMU functions are generated by dedicated, on-chip, 16-bit DACs. To facilitate accurate level programming, the ADATE334 includes an integrated calibration function that corrects gain and offset errors of each functional block. Correction coefficients can be stored on-chip, and any values written to the DACs automatically adjust using the appropriate correction factors.The ADATE334 uses a serial programmable interface (SPI) bus to program all functional blocks, DACs, and on-chip calibration constants. The ADATE334 has an on-chip temperature sensor to monitor temperature and overvoltage and undervoltage alarms that monitor and report any output pin or transient PPMU voltage faults that can occur during operation. The ADATE334 also provides a per channel, open-drain relay driver.For more information on the ADATE334, contact ADATE334@anlaog.com.

The ADAU1372 is a codec with four inputs and two outputs, which incorporates asynchronous sample rate converters. Optimized for low latency and low power, the ADAU1372 is ideal for headsets, handsets, and headphones. The ADAU1372 has built-in programmable gain amplifiers (PGAs); thus, with the addition of just a few passive components and a crystal, the ADAU1372 provides a solution for headset audio needs. Microphone preamplifiers, ADCs, DACs, headphone amplifiers and serial ports for connections to an external DSP.APPLICATIONS Handsets, headsets, and headphones Bluetooth handsets, headsets, and headphones Personal navigation devices Digital still and video cameras

The ADAU1452 /?ADAU1451?/?ADAU1450 are automotive qualified audio processors that far exceed the digital signal processing capabilities of earlier SigmaDSP? devices. The restructured hardware architecture is optimized for efficient audio processing. The audio processing algorithms are realized in sample-by-sample and block-by-block paradigms that can both be executed simultaneously in a signal processing flow created using the graphical programming tool, SigmaStudio?. The restructured digital signal processor (DSP) core architecture enables some types of audio processing algorithms to be executed using significantly fewer instructions than were required on previous SigmaDSP generations, leading to vastly improved code efficiency.The 1.2 V, 32-bit DSP core can run at frequencies of up to 294.912 MHz and execute up to 6144 instructions per sample at the standard sample rate of 48 kHz. However, in addition to industry-standard rates, a wide range of sample rates are available. The integer PLL and flexible clock generator hardware can generate up to 15 audio sample rates simultaneously. These clock generators, along with the on-board asynchronous sample rate converters (ASRCs) and a flexible hardware audio routing matrix, make the ADAU1452 / ADAU1451 / ADAU1450 ideal audio hubs that greatly simplify the design of complex multirate audio systems.The ADAU1452 / ADAU1451 / ADAU1450 interface with a wide range of analog-to-digital converters (ADCs), digital-to-analog converters (DACs), digital audio devices, amplifiers, and control circuitry, due to their highly configurable serial ports, S/PDIF interfaces (on the ADAU1452 and ADAU1451), and multipurpose input/output pins. The devices can also directly interface with pulse density modulation (PDM) output microelectromechanical (MEMS) microphones, due to integrated decimation filters specifically designed for that purpose.Independent slave and master I2C/serial peripheral interface (SPI) control ports allow the ADAU1452 / ADAU1451 / ADAU1450 not only to be programmed and configured by an external master device, but also to act as masters that can program and configure external slave devices directly. This flexibility, combined with self boot functionality, enables the design of standalone systems that do not require any external input to operate.The power efficient DSP core executes full programs, consumes only a few hundred milliwatts (mW) of power, and can run at a maximum program load while consuming less than a watt, even in worst case temperatures exceeding 100?C. This relatively low power consumption and small footprint make the ADAU1452 / ADAU1451 / ADAU1450 ideal replacements for large, general-purpose DSPs that consume more power at the same processing load.Differences between the ADAU1452, ADAU1451, and ADAU1450The five variants of this device are differentiated by memory, DSP core frequency, availability of S/PDIF interfaces, ASRC configuration, and temperature range.Because the ADAU1450 does not contain an S/PDIF receiver or transmitter, the SPDIFIN and SPDIFOUT pins are nonfunctional. Additionally, the settings of any registers related to the S/PDIF input or output in the ADAU1450 do not have any effect on the operation of the device.Because the ADAU1450 does not contain ASRCs, the settings of any registers related to the ASRCs in the ADAU1450 do not have any effect on the operation of the device.APPLICATIONS Automotive audio processing Head units Navigation systems Rear seat entertainment systems DSP amplifiers (sound system amplifiers) Commercial and professional audio processing Consumer audio processing

The ADAU1977 incorporates four high performance analog-to-digital converters (ADCs) with direct-coupled inputs capable of 10 V rms. The ADC uses multibit sigma-delta (?-?) architecturewith continuous time front end for low EMI. The ADCs can be connected to the electret microphone (ECM) directly and provide the bias for powering the microphone. Built-in diagnostic circuitry detects faults on input lines and includes comprehensive diagnostics for faults on microphone inputs. The faults reported are short to battery, short to microphone bias, short to ground, short between positive and negative input pins, and open input terminals. In addition, each diagnostic fault is available as an IRQ flag for ease in system design. An I2C/SPI control port is also included. The ADAU1977 uses only a single 3.3 V supply. The part internally generates the microphone bias voltage. The microphone bias is programmable in a few steps from 5 V to 9 V. The low power architecture reduces the power consumption. An on-chip PLL can derive the master clock from an external clock input or frame clock (sample rate clock). When fed with a frame clock, the PLL eliminates the need for a separate high frequency master clock in the system. The ADAU1977 is available in a 40-lead LFCSP package.APPLICATIONS Automotive audio systems Active Noise Cancellation System

The ADAU7002 converts a stereo PDM bit stream into a PCMoutput. The source for the PDM data can be two microphonesor other PDM sources. The PCM audio data is output on aserial audio interface port in either I2S or TDM format.The ADAU7002 is specified over the commercial temperaturerange (?40?C to +85?C). It is available in a halide-free, 8-ball,1.56 mm ? 0.76 mm, wafer level chip scale package (WLCSP).Applications Mobile computing Portable electronics Consumer electronics

The ADBMS6830 is a multicell battery stack monitor that measures up to 16 series connected battery cells with a lifetime total measurement error (TME) of less than 2 mV over the full temperature range. The measurement input range of ?2 V to +5.5 V makes the ADBMS6830 suitable for most battery chemistries and allows measurement of voltages across bus bars. Provisions are made for bypassing bus bars without dedicating any measurement channels.All cells can be measured simultaneously and redundantly with two individual analog-to-digital converters (ADCs). The continuously operating ADCs with a high sampling rate of 4.096 MHz allow reduced external analog filtering and aliasing free measurement results. Higher noise reduction can be achieved by subsequent programmable infinite impulse response (IIR) filters.Multiple ADBMS6830s can be connected in series, permitting simultaneous cell monitoring of long, high voltage battery strings.Each ADBMS6830 has an isolated serial port interface (isoSPI?) for high speed, RF immune, long distance communications. Multiple devices are connected in a daisy chain with one host processor connection. This daisy chain can be operated bidirectionally, ensuring communication integrity even in the event of a fault along the communication path.The ADBMS6830 can be powered from the battery stack or an isolated supply. The ADBMS6830 includes passive balancing with individual pulse-width modulation (PWM) duty cycle control and up to 300 mA discharge current for each cell. Other features include an on-board 5 V regulator, up to 10 general-purpose inputs/outputs, and a sleep mode, where current consumption is reduced to 4 ?A.APPLICATIONS Electric and hybrid electric vehicles Backup battery systems Grid energy storage

The ADCMP561/ADCMP562 are high speed comparators fabricated on Analog Devices, Inc., proprietary XFCB process. The devices feature a 700 ps propagation delay with less than 75 ps overdrive dispersion. Dispersion, a measure of the difference in propagation delay under differing overdrive conditions, is a particularly important characteristic of comparators. A separate programmable hysteresis pin is available on the ADCMP562.A differential input stage permits consistent propagation delay with a wide variety of signals in the common-mode range from ?2.0 Vto +3.0 V. Outputs are complementary digital signals that are fully compatible with PECL 10 K and 10 KH logic families. The outputs provide sufficient drive current to directly drive transmission lines terminated in 50 ? to VDD ? 2 V. A latch input, which is included, permits tracking, track-and-hold, or sample-and-hold modes of operation. The latch input pins contain internal pull-ups that set the latch in tracking mode when left open.The ADCMP561/ADCMP562 are specified over the industrial temperature range (?40?C to +85?C).Applications Automatic test equipment High speed instrumentation Scope and logic analyzer front ends Window comparators High speed line receivers Threshold detection Peak detection High speed triggers Patient diagnostics Disk drive read channel detection Hand-held test instruments Zero-crossing detectors Line receivers and signal restoration Clock drivers

The ADCMP572?and ADCMP573 are ultrafast comparators fabricated on Analog Devices? proprietary XFCB3 Silicon Germanium (SiGe) bipolar process. The ADCMP572 features CML output drivers and latch inputs, and the ADCMP573 features reduced swing PECL (RSPECL) output drivers and latch inputs.Both devices offer 150 ps propagation delay and 80 ps minimum pulse width for 10 Gbps operation with 200 fs rms random jitter (RJ). Overdrive and slew rate dispersion are typically less than 15 ps.A flexible power supply scheme allows both devices to operate with a single 3.3 V positive supply and a ?0.2 V to +1.2 V input signal range or with split input/output supplies to support a wider ?0.2 V to +3.2 V input signal range and an independent range of output levels. 50 ? on-chip termination resistors are provided at both inputs with the optional capability to be left open (on an individual pin basis) for applications requiring high impedance inputs.The CML output stage is designed to directly drive 400 mV into 50 ? transmission lines terminated to between 3.3 V to 5.2 V. The RSPECL output stage is designed to drive 400 mV into 50 ? terminated to VCCO ? 2 V and is compatible with several commonly used PECL logic families. The comparator input stage offers robust protection against large input overdrive, and the outputs do not phase reverse when the valid input signal range is exceeded. High speed latch and programmable hysteresis features are also provided.The ADCMP572 and ADCMP573 are available in a 16-lead LFCSP package and have been characterized over an extended industrial temperature range of ?40?C to +125?C.APPLICATIONS Clock and data signal restoration and level shifting Automatic test equipment (ATE) High speed instrumentation Pulse spectroscopy Medical imaging and diagnostics High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry

The ADCMP580/ADCMP581/ADCMP582 are ultrafast voltagecomparators fabricated on the Analog Devices, Inc. proprietaryXFCB3 Silicon Germanium (SiGe) bipolar process. TheADCMP580 features CML output drivers, the ADCMP581features reduced swing ECL (negative ECL) output drivers, andthe ADCMP582 features reduced swing PECL (positive ECL)output drivers.All three comparators offer 180 ps propagation delay and 100 psminimum pulse width for 10 Gbps operation with 200 fs randomjitter (RJ). Overdrive and slew rate dispersion are typically lessthan 15 ps.The ?5 V power supplies enable a wide ?2 V to +3 V inputrange with logic levels referenced to the CML/NECL/PECLoutputs. The inputs have 50 ? on-chip termination resistorswith the optional capability to be left open (on an individualpin basis) for applications requiring high impedance input. The CML output stage is designed to directly drive 400 mV into50 ? transmission lines terminated to ground. The NECL outputstages are designed to directly drive 400 mV into 50 ? terminatedto ?2 V. The PECL output stages are designed to directly drive400 mV into 50 ? terminated to VCCO ? 2 V. High speed latchand programmable hysteresis are also provided. The differentiallatch input controls are also 50 ? terminated to an independentVTT pin to interface to either CML or ECL or to PECL logic.The ADCMP580/ADCMP581/ADCMP582 are available in a16-lead LFCSP.Applications Automatic test equipment (ATE) High speed instrumentation Pulse spectroscopy Medical imaging and diagnostics High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry Clock and data signal restoration

The EVAL-ADE1202EBZ is a full featured evaluation board, designed to allow the user to easily evaluate the ADE1202 dual-channel, configurable, isolated digital binary input IC performance in a context similar to a real binary input interface application. The evaluation kit requires purchasing the controller board for the system demonstration platform (EVAL-SDP-CB1Z). The evaluation kit includes evaluation software, written in LabVIEW®, which provides access to the registers and features of the device through a PC interface. Consult the ADE1202 data sheet in conjunction with this user guide when using the EVAL-ADE1202EBZ.

The ADE9430 is a highly accurate, fully integrated, polyphase energy and power quality monitoring device. Superior analog performance and a digital signal processing (DSP) core enable accurate energy monitoring over a wide dynamic range. An integrated high end reference ensures low drift over temperature with a combined drift of less than ?25 ppm/?C maximum for the entire channel including a programmable gain amplifier (PGA) and an analog-to-digital converter (ADC).The ADE9430 offers a complete power quality monitoring capability by providing instantaneous total as well as fundamental measurements on rms, frequency, phase angle, power factor active, reactive, and apparent powers and energies. Using the optional ADSWPQ-CLS Power Quality Library, advanced power quality features, such as dip and swell monitoring, power frequency, voltage total harmonic distortion (VTHD), and current total harmonic distortion (ITHD), are enabled. The one cycle rms, 10 cycle rms/12 cycle rms, and the optional ADSW-PQ-CLS Power Quality Library features are calculated according to IEC 61000-4-30 Class S. To request access to the ADSW-PQ-CLS, fill out the software request form at: Software Request Form | Analog Devices, where the target technology must be power quality monitoring and the processor/system on chip (SoC) is the ADE9430.The ADE9430 offers a resampled waveform of 1024 points per 10 cycles or 12 cycles. Resampling simplifies the fast Fourier transform (FFT) calculation of at least 40 harmonics in an external processor.The ADE9430 simplifies the implementation and certification of energy and power quality monitoring systems by providing tight integration of acquisition and calculation engines. The integrated ADCs and DSP engine calculate various parameters and provide data through user accessible registers or indicate events through interrupt pins. With seven dedicated ADC channels, the ADE9430 can be used on a 3-phase system or up to three single-phase systems. This device supports current transformers (CTs) or Rogowski coils when used with external analog integrator for current measurements.The ADE9430 absorbs most of the complexity in calculations for a power quality monitoring system. Combining a simple host microcontroller and the optional ADSW-PQ-CLS Power Quality Library, the ADE9430 enables the design of standalone monitoring or protection systems, or low cost nodes uploading data into the cloud.APPLICATIONS Energy and power monitoring Standards compliant power quality monitoring Protective devices Machine health Smart power distribution units Polyphase energy meters

The ADF5002 prescaler is a low noise, low power, fixed RF divider block that can be used to divide down frequencies as high as 18 GHz to a lower frequency suitable for input to a PLL IC, such as the ADF4156 or the ADF4106. The ADF5002 provides a divide-by-8 function. The ADF5002 operates from a 3.3 V supply and has differential 100 ? RF outputs to allow direct interface to the differential RF inputs of PLLs such as the ADF4156 and ADF4106.ApplicationsPLL frequency range extenderPoint-to-point radiosVSAT radiosCommunications test equipment

The ADF7021 is a low power, highly integrated 2FSK/3FSK/4FSK transceiver. It is designed to operate in the narrowband, license-free ISM bands and licensed bands in the 80 MHz to 650 MHz and 862 MHz to 940 MHz frequency ranges. It has both Gaussian and raised cosine data filtering options to improve spectral efficiency for narrowband applications.It is suitable for circuit applications targeted at European ETSI-EN 300-220, the Japanese ARIB STD-T67, the Chinese Short Range Device regulations, and the North American FCC Part 15, Part 90, and Part 95 regulatory standards. A complete transceiver can be built using a small number of external discrete components, making the ADF7021 very suitable for price-sensitive and area-sensitive applications.The transmit section contains a voltage controlled oscillator (VCO) and a low noise fractional-N PLL with output resolution of

The ADF7021-N is a high performance, low power, narrow-band transceiver based on the ADF7021. The ADF7021-N has IF filter bandwidths of 9 kHz, 13.5 kHz, and 18.5 kHz, making it ideally suited to worldwide narrowband standards and particularly those that stipulate 12.5 kHz channel separation. It is designed to operate in the narrow-band, license-free ISM bands and in the licensed bands with frequency ranges of 80 MHz to 650 MHz and 842 MHz to 916 MHz. The part has both Gaussian and raised cosine transmit data filtering options to improve spectral efficiency for narrow-band applications. It is suitable for circuit applications targeted at the Japanese ARIB STD-T67, the European ETSI EN 300 220, the Korean short range device regulations, the Chinese short range device regulations, and the North American FCC Part 15, Part 90, and Part 95 regulatory standards. A complete transceiver can be built using a small number of external discrete components, making the ADF7021-N very suitable for price-sensitive and area-sensitive applications. The range of on-chip FSK modulation and data filtering options allows users greater flexibility in their choice of modulation schemes while meeting the tight spectral efficiency requirements. The ADF7021-N also supports protocols that dynamically switch among 2FSK, 3FSK, and 4FSK to maximize communica-tion range and data throughput. The transmit section contains two voltage controlled oscillators (VCOs) and a low noise fractional-N PLL with an output resolution of The frequency-agile PLL allows the ADF7021-N to be used in frequency-hopping, spread spectrum (FHSS) systems. Both VCOs operate at twice the fundamental frequency to reduce spurious emissions and frequency pulling problems. The transmitter output power is programmable in 63 steps from ?16 dBm to +13 dBm and has an automatic power ramp control to prevent spectral splatter and help meet regulatory standards. The transceiver RF frequency, channel spacing, and modulation are programmable using a simple 3-wire interface. The device operates with a power supply range of 2.3 V to 3.6 V and can be powered down when not in use. A low IF architecture is used in the receiver (100 kHz), which minimizes power consumption and the external component count yet avoids dc offset and flicker noise at low frequencies. The IF filter has programmable bandwidths of 9 kHz, 13.5 kHz, and 18.5 kHz. The ADF7021-N supports a wide variety of pro-grammable features including Rx linearity, sensitivity, and IF bandwidth, allowing the user to trade off receiver sensitivity and selectivity against current consumption, depending on the application. The receiver also features a patent-pending automatic frequency control (AFC) loop with programmable pull-in range that allows the PLL to track out the frequency error in the incoming signal. The receiver achieves an image rejection performance of 56 dB using a patent-pending IR calibration scheme that does not require the use of an external RF source. An on-chip ADC provides readback of the integrated tempera-ture sensor, external analog input, battery voltage, and RSSI signal, which provides savings on an ADC in some applications. The temperature sensor is accurate to ?10?C over the full oper-ating temperature range of ?40?C to +85?C. This accuracy can be improved by performing a 1-point calibration at room temperature and storing the result in memory.

The ADF7023-J is a very low power, high performance, highly integrated 2FSK/GFSK/MSK/GMSK transceiver designed for operation in the 902 MHz to 958 MHz frequency band, which covers the ARIB Standard T96 band at 950 MHz. Data rates from 1 kbps to 300 kbps are supported.The transmit RF synthesizer contains a VCO and a low noise fractional-N phase locked loop (PLL) with an output channel frequency resolution of 400 Hz. The VCO operates at twice the fundamental frequency to reduce spurious emissions. The receive and transmit synthesizer bandwidths are automatically, and independently, configured to achieve optimum phase noise, modulation quality, and settling time. The transmitter output power is programmable from ?20 dBm to +13.5 dBm, with automatic PA ramping to meet transient spurious specifications. The part possesses both single-ended and differential PAs, which allow for Tx antenna diversity.The receiver is exceptionally linear, achieving an IP3 specification of ?12.2 dBm and ?11.5 dBm at maximum gain and minimum gain, respectively, and an IP2 specification of 18.5 dBm and 27 dBm at maximum gain and minimum gain, respectively. The receiver achieves an interference blocking specification of 66 dB at a ?2 MHz offset and 74 dB at a ?10 MHz offset. Thus, the part is extremely resilient to the presence of interferers in spectrally noisy environments. The receiver features a novel, high speed, AFC loop, allowing the PLL to find and correct any RF frequency errors in the recovered packet. A patent pending image rejection calibration scheme is available by downloading the image rejection calibration firmware module to program RAM. The algorithm does not require the use of an external RF source nor does it require any user intervention once initiated. The results of the calibration can be stored in nonvolatile memory for use on subsequent power-ups of the transceiver.See data sheet for additional information.Applications Smart metering IEEE 802.15.4g Home automation Process and building control Home Energy Management Systems (HEMS) Wireless sensor networks (WSNs) Wireless healthcare

The ADF7024 is an ultralow power, integrated transceiver for use in the license-free ISM bands at 433 MHz, 868 MHz, and 915 MHz. Its ease of use and high performance make it suitable for a wide variety of wireless applications. The ADF7024 is suitable for operation under the European ETSI EN 300-220 regulation, the North American FCC Part 15 regulation, and other similar regulatory standards.The ADF7024 can operate under a number of predefined radio profiles. For each radio profile, optimized register settings are provided for the ADF7024 radio. This ensures that the RF communication layer works seamlessly, allowing the user to concentrate on the protocol and system level design and prototyping. The radio profiles cover common data rate and modulation options. There are six radio profiles in total, as shown in Table 1.The ADF7024 operates with a power supply range of 2.2 V to 3.6 V and has very low power consumption in both Tx and Rx modes, enabling long lifetimes in battery-operated systems while maintaining excellent RF performance.The low IF receiver minimizes power consumption and provides excellent sensitivity. The receiver is exceptionally linear and, therefore, is very resilient to the presence of interferers in spectrally noisy environments. The highly efficient transmitter has programmable output power up to 13.5 dBm and automatic power amplifier (PA) ramping to meet transient spurious specifications. The RF synthesizer comprises a voltage controlled oscillator (VCO), a low noise fractional-N phase-locked loop (PLL) and a loop filter, all of which are fully integrated and automatically calibrated. This agile frequency synthesizer facilitates the implementation of frequency-hopping spread spectrum (FHSS) systems.The smart wake mode (SWM) allows the ADF7024 to wake up autonomously from sleep using the internal wake-up timer without intervention from the host processor. This functionality allows carrier sense, packet sniffing, and packet reception while the host processor is in sleep, thereby reducing overall system current consumption.The ADF7024 eases the processing burden of the host processor by integrating the lower layers of a typical communication protocol stack. The host processor can configure the ADF7024 using a simple command-based protocol over a standard 4-wire SPI interface. A single-byte command transitions the radio between states or performs a radio function.A complete wireless solution can be built using a small number of external discrete components and a host processor (typically a microcontroller).For more information, see the ADF7024 Hardware Reference Manual, UG-698, which is only available as part of the ADF7024 design resource package.APPLICATIONS Wireless sensor networks (WSNs) Home and building automation Asset tracking Process and building control Industrial control Internet of Things (IoT)

The ADF9010 is a fully integrated RF Tx modulator and Rx analog baseband front end that operates in the frequency range from 840 MHz to 960 MHz. The receive path consists of a fully differential I/Q baseband PGA, low-pass filter, and general signal conditioning before connecting to an Rx ADC for baseband conversion. The Rx LPF gain ranges from 3 dB to 24 dB, programmable in 3 dB steps. The Rx LPF features four programmable modes with cutoff frequencies of 330 kHz, 880 kHz, and 1.76 MHz, or the filter can be bypassed if necessary.The transmit path consists of a fully integrated differential Tx direct I/Q upconverter with a high linearity PA driver amplifier. It converts a baseband I/Q signal to an RF carrier-based signal between 840 MHz and 960 MHz. The highly linear transmit signal path ensures low output distortion.Complete local oscillator (LO) signal generation is integrated on chip, including the integer-N synthesizer and VCO, which generate the required I and Q signals for transmit I/Q upconversion. The LO signal is also available at the output to drive an external RF demodulator. Control of all the on-chip registers is via a simple 3-wire serial interface. The device operates with a power supply ranging from 3.15 V to 3.45 V and can be powered down when not in use.APPLICATIONS 900 MHz RFID readers Unlicensed band 900 MHz applications