The ADF7021-V is a high performance, low power, narrow-band RF transceiver based on the ADF7021-N. The architecture of the ADF7021-V transceiver is similar to that of the ADF7021-N except that an external VCO is used by the on-chip RF synthesizer for applications that require improved phase noise performance.The ADF7021-V is designed to operate in both the license-free ISM bands and in the licensed bands from 80 MHz to 960 MHz.To minimize RF feedthrough and spurious emissions, the external VCO operates at 2? or 4? the desired RF frequency; the ADF7021-V supports a maximum VCO frequency operation of 1920 MHz. The 4? VCO operation is programmable by enabling an additional on-chip divide-by-2 outside the RF synthesizer loop and offers improved phase noise performance.As with the ADF7021-N receiver, the IF filter bandwidths of 9 kHz, 13.5 kHz, and 18.5 kHz are supported, making the ADF7021-V ideally suited to worldwide narrow-band telemetry applications.The part has both Gaussian and raised cosine transmit data filtering options to improve spectral efficiency for narrow-band applications. It is suitable for circuit applications targeted at the following: European ETSI EN 300 220 North American FCC Part 15, Part 90, and Part 95 Japanese ARIB STD-T67 Korean short-range device regulations Chinese short-range device regulationsA complete transceiver can be built using a small number of discrete external components, making the ADF7021-V very suitable for area-sensitive, high performance driven applications.See data sheet for more information.APPLICATIONS Narrow-band, short range device (SRD) standards ETSI EN 300 220 FCC Part 90 (meets Emission Mask D requirements) FCC Part 95 ARIB STD-T67 Wireless Metering Narrow-band wireless telemetry

The ADF7024 is an ultralow power, integrated transceiver for use in the license-free ISM bands at 433 MHz, 868 MHz, and 915 MHz. Its ease of use and high performance make it suitable for a wide variety of wireless applications. The ADF7024 is suitable for operation under the European ETSI EN 300-220 regulation, the North American FCC Part 15 regulation, and other similar regulatory standards.The ADF7024 can operate under a number of predefined radio profiles. For each radio profile, optimized register settings are provided for the ADF7024 radio. This ensures that the RF communication layer works seamlessly, allowing the user to concentrate on the protocol and system level design and prototyping. The radio profiles cover common data rate and modulation options. There are six radio profiles in total, as shown in Table 1.The ADF7024 operates with a power supply range of 2.2 V to 3.6 V and has very low power consumption in both Tx and Rx modes, enabling long lifetimes in battery-operated systems while maintaining excellent RF performance.The low IF receiver minimizes power consumption and provides excellent sensitivity. The receiver is exceptionally linear and, therefore, is very resilient to the presence of interferers in spectrally noisy environments. The highly efficient transmitter has programmable output power up to 13.5 dBm and automatic power amplifier (PA) ramping to meet transient spurious specifications. The RF synthesizer comprises a voltage controlled oscillator (VCO), a low noise fractional-N phase-locked loop (PLL) and a loop filter, all of which are fully integrated and automatically calibrated. This agile frequency synthesizer facilitates the implementation of frequency-hopping spread spectrum (FHSS) systems.The smart wake mode (SWM) allows the ADF7024 to wake up autonomously from sleep using the internal wake-up timer without intervention from the host processor. This functionality allows carrier sense, packet sniffing, and packet reception while the host processor is in sleep, thereby reducing overall system current consumption.The ADF7024 eases the processing burden of the host processor by integrating the lower layers of a typical communication protocol stack. The host processor can configure the ADF7024 using a simple command-based protocol over a standard 4-wire SPI interface. A single-byte command transitions the radio between states or performs a radio function.A complete wireless solution can be built using a small number of external discrete components and a host processor (typically a microcontroller).For more information, see the ADF7024 Hardware Reference Manual, UG-698, which is only available as part of the ADF7024 design resource package.APPLICATIONS Wireless sensor networks (WSNs) Home and building automation Asset tracking Process and building control Industrial control Internet of Things (IoT)

The ADF7024 is an ultralow power, integrated transceiver for use in the license-free ISM bands at 433 MHz, 868 MHz, and 915 MHz. Its ease of use and high performance make it suitable for a wide variety of wireless applications. The ADF7024 is suitable for operation under the European ETSI EN 300-220 regulation, the North American FCC Part 15 regulation, and other similar regulatory standards.The ADF7024 can operate under a number of predefined radio profiles. For each radio profile, optimized register settings are provided for the ADF7024 radio. This ensures that the RF communication layer works seamlessly, allowing the user to concentrate on the protocol and system level design and prototyping. The radio profiles cover common data rate and modulation options. There are six radio profiles in total, as shown in Table 1.The ADF7024 operates with a power supply range of 2.2 V to 3.6 V and has very low power consumption in both Tx and Rx modes, enabling long lifetimes in battery-operated systems while maintaining excellent RF performance.The low IF receiver minimizes power consumption and provides excellent sensitivity. The receiver is exceptionally linear and, therefore, is very resilient to the presence of interferers in spectrally noisy environments. The highly efficient transmitter has programmable output power up to 13.5 dBm and automatic power amplifier (PA) ramping to meet transient spurious specifications. The RF synthesizer comprises a voltage controlled oscillator (VCO), a low noise fractional-N phase-locked loop (PLL) and a loop filter, all of which are fully integrated and automatically calibrated. This agile frequency synthesizer facilitates the implementation of frequency-hopping spread spectrum (FHSS) systems.The smart wake mode (SWM) allows the ADF7024 to wake up autonomously from sleep using the internal wake-up timer without intervention from the host processor. This functionality allows carrier sense, packet sniffing, and packet reception while the host processor is in sleep, thereby reducing overall system current consumption.The ADF7024 eases the processing burden of the host processor by integrating the lower layers of a typical communication protocol stack. The host processor can configure the ADF7024 using a simple command-based protocol over a standard 4-wire SPI interface. A single-byte command transitions the radio between states or performs a radio function.A complete wireless solution can be built using a small number of external discrete components and a host processor (typically a microcontroller).For more information, see the ADF7024 Hardware Reference Manual, UG-698, which is only available as part of the ADF7024 design resource package.APPLICATIONS Wireless sensor networks (WSNs) Home and building automation Asset tracking Process and building control Industrial control Internet of Things (IoT)

The ADG1634L is a monolithic industrial CMOS (iCMOS?) analog switch comprising four independently selectable single-pole, double-throw (SPDT) switches, respectively.All channels exhibit break-before-make switching action that prevents momentary shorting when switching channels. An EN input on the ADG1634L is used to enable or disable the device. When disabled, all channels are switched off. The switch is enabled with a Logic 1 EN input, while the INx input defines the state of the SPDT switch (see Table 12 in the data sheet).The ultralow on resistance and on-resistance flatness of the switch makes it an ideal solution for data acquisition and gain switching applications, where low distortion is critical. iCMOS construction ensures ultra low power dissipation, making the device ideally suited for portable and battery-powered instruments.An external VL supply provides flexibility for lower logic control. The ADG1634L is both 1.2 V and 1.8 V JEDEC standard compliant.APPLICATIONS Communication systems Medical systems Audio signal routing Video signal routing Automatic test equipment Data acquisition systems Battery-powered systems FPGA and microcontroller systems Sample-and-hold systems Relay replacementsPRODUCT HIGHLIGHTS 8.2 ? maximum on resistance over temperature. Minimum distortion. VL supply for low logic level compatibility. JEDEC standard compliant for both 1.2 V and 1.8 V logic levels. Guaranteed switch off when digital inputs are floating. 24-lead, 4 mm ? 4 mm LFCSP.

The ADGS1208/ADGS1209 are analog multiplexers comprisingeight single channels and four differential channels, respectively. Aserial peripheral interface (SPI) controls the switches. The SPIinterface has robust error detection features, such as cyclicredundancy check (CRC) error detection, invalid read/writeaddress detection, and SCLK count error detection.It is possible to daisy-chain multiple ADGS1208/ADGS1209devices together. Daisy-chain mode enables the configuration ofmultiple devices with a minimal amount of digital lines. TheADGS1208/ADGS1209 can also operate in burst mode todecrease the time between SPI commands.iCMOS? construction ensures ultralow power dissipation,making the devices ideally suited for portable and batterypoweredinstruments.Each switch conducts equally well in both directions when on,and each switch has an input signal range that extends to thesupplies. In the off condition, signal levels up to the suppliesare blocked. The ultralow on capacitance (CON) and exceptionally low chargeinjection (QINJ) of these multiplexers make them ideal solutionsfor data acquisition and sample-and-hold applications, wherelow glitch and fast settling are required.Product Highlights SPI interface removes the need for parallel conversion, logic traces and reduces GPIO channel count. Daisy-chain mode removes additional logic traces when multiple devices are used. CRC error detection, invalid read/write address detection, and SCLK count error detection ensures a robust digital interface. CRC and Error detection capabilities allows for the use of the ADGS1208/ADGS1209 in safety critical systems.Applications Audio and video routing Automatic test equipment Data-acquisition systems Battery-powered systems Sample-and-hold systems Communication systems

The ADGS1208/ADGS1209 are analog multiplexers comprisingeight single channels and four differential channels, respectively. Aserial peripheral interface (SPI) controls the switches. The SPIinterface has robust error detection features, such as cyclicredundancy check (CRC) error detection, invalid read/writeaddress detection, and SCLK count error detection.It is possible to daisy-chain multiple ADGS1208/ADGS1209devices together. Daisy-chain mode enables the configuration ofmultiple devices with a minimal amount of digital lines. TheADGS1208/ADGS1209 can also operate in burst mode todecrease the time between SPI commands.iCMOS? construction ensures ultralow power dissipation,making the devices ideally suited for portable and batterypoweredinstruments.Each switch conducts equally well in both directions when on,and each switch has an input signal range that extends to thesupplies. In the off condition, signal levels up to the suppliesare blocked. The ultralow on capacitance (CON) and exceptionally low chargeinjection (QINJ) of these multiplexers make them ideal solutionsfor data acquisition and sample-and-hold applications, wherelow glitch and fast settling are required.Product Highlights SPI interface removes the need for parallel conversion, logic traces and reduces GPIO channel count. Daisy-chain mode removes additional logic traces when multiple devices are used. CRC error detection, invalid read/write address detection, and SCLK count error detection ensures a robust digital interface. CRC and Error detection capabilities allows for the use of the ADGS1208/ADGS1209 in safety critical systems.Applications Audio and video routing Automatic test equipment Data-acquisition systems Battery-powered systems Sample-and-hold systems Communication systems

The ADIN1200 is a low power, single-port, 10 Mbps and 100 Mbps Ethernet transceiver with low latency specifications designedfor industrial Ethernet applications.This design integrates an energy efficient Ethernet (EEE) physical layer device (PHY) core with all associated common analog circuitry, input and output clock buffering, management interface and subsystem registers, and media access control (MAC) interface and control logic to manage the reset, clock control and pin configuration.The ADIN1200 is available in a 5 mm ? 5 mm, 32-lead leadframe chip scale package (LFCSP) and can operate with a single3.3 V supply, assuming the use of a 3.3 V MAC interface supply.For maximum flexibility in system level design, a separate VDDIOsupply enables the management data input/output (MDIO) andMAC interface supply voltages to be configured independentlyof the other circuitry on the ADIN1200 allowing operation at1.8 V, 2.5 V, or 3.3 V. At power-up, the ADIN1200 is held inhardware reset until each of the supplies has crossed its minimumrising threshold value and the power is considered good. Brownoutprotection is provided by monitoring the supplies to detect ifone or more of them drops below a minimum falling thresholdand holding the device in hardware reset until the power suppliesreturn and satisfy the power-on-reset (POR) circuit.The MII management interface (also referred to as MDIOinterface) provides a 2-wire serial interface between a hostprocessor or MAC and the ADIN1200, allowing access tocontrol and status information in the PHY core managementregisters. The interface is compatible with both IEEE? 802.3?Standard Clause 22 and Clause 45 management framestructures.The ADIN1200 can support cable lengths up to 180 meters.Note that throughout this data sheet, multifunction pins, such as XTAL_I/CLK_IN/REF_CLK, are referred to either by the entire pin name or by a single function of the pin, for example, XTAL_I, when only that function is relevant.Applications Industrial automation Process control Factory automation Robotics and motion Control Building automation Test and Measurement Industrial internet of things (IoT)

The ADIN1300 is a low power, single port, Gigabit Ethernet transceiver with low latency and power consumption specifications primarily designed for industrial Ethernet applications.This design integrates an energy efficient Ethernet (EEE) physical layer device (PHY) core with all associated common analog circuitry, input and output clock buffering, management interface and subsystem registers, and MAC interface and control logic to manage the reset and clock control and pin configuration.The ADIN1300 is available in a 6 mm ? 6 mm, 40-lead lead frame chip scale package (LFCSP). The device operates with a minimum of 2 power supplies, 0.9 V and 3.3 V, assuming the use of a 3.3 V MAC interface supply. For maximum flexibility in system level design, a separate VDDIO supply enables the management data input/output (MDIO) and MAC interface supply voltages to be configured independently of the other circuitry on the ADIN1300, allowing operation at 1.8 V, 2.5 V, or 3.3 V. At power-up, the ADIN1300 is held in hardware reset until each of the supplies has crossed its minimum rising threshold value. Brown-out protection is provided by monitoring the supplies to detect if one or more supply drops below a minimum falling threshold (see Table 17 on the datasheet), and holding the device in hardware reset until the power supplies return and satisfy the power-on reset (POR) circuit.The MII management interface (also referred to as MDIO interface) provides a 2-wire serial interface between a host processor or MAC (also known as management station (STA)) and the ADIN1300, allowing access to control and status information in the PHY core management registers. The interface is compatible with both the IEEE 802.3 Standard Clause 22 and Clause 45 management frame structures.The ADIN1300 can support cable lengths up to 150 meters at Gigabit speeds and 180 meters when operating at 100 Mbps or 10 Mbps.Applications Industrial automation Process control Factory automation Robotics/Motion Control Building automation Test and Measurement Industrial IoT

The ADM1063 is a configurable supervisory/sequencing device that offers a single-chip solution for supply monitoring and sequencing in multiple supply systems. In addition to these functions, the ADM1063 integrates a 12-bit ADC that can be used to accurately read back up to 12 separate voltages.The device also provides up to 10 programmable inputs for monitoring under, over, or out-of-window faults on up to 10 supplies. In addition, 10 programmable outputs can be used as logic enables. Six of these programmable outputs can provide up to a 12 V output for driving the gate of an n-FET that can be placed in the path of a supply.ApplicationsCentral office systems Servers/routers Multivoltage system line cards DSP/FPGA supply sequencing In-circuit testing of margined supplies

PCM1862 103-dB; 2-channel; software-controlled; audio ADC with universal front end evaluation module

TLV1117LV evaluation module for 1-A; fixed-voltage; LDO linear regulator

The ADV7180 automatically detects and converts standard analog baseband television signals compatible with worldwide NTSC, PAL, and SECAM standards into 4:2:2 component video data compatible with the 8-bit ITU-R BT.656 interface standard.The simple digital output interface connects gluelessly to a wide range of MPEG encoders, codecs, mobile video processors, and Analog Devices, Inc., digital video encoders, such as the ADV7391. External HS, VS, and FIELD signals provide timing references for LCD controllers and other video ASICs, if required. Accurate 10-bit analog-to-digital conversion provides professional quality video performance for consumer applications with true 8-bit data resolution. Three analog video input channels accept standard composite, S-video, or component video signals, supporting a wide range of consumer video sources. AGC and clamp-restore circuitry allow an input video signal peak-to-peak range to 1.0 V. Alternatively, these can be bypassed for manual settings.The line-locked clock output allows the output data rate, timing signals, and output clock signals to be synchronous, asynchronous, or line locked even with ?5% line length variation. Output control signals allow glueless interface connections in many applications. The ADV7180 is programmed via a 2-wire, serial bidirectional port (I2C? compatible) and is fabricated in a 1.8 V CMOS process. Its monolithic CMOS construction ensures greater functionality with lower power dissipation. LFCSP package options makes the decoder ideal for space-constrained portable applications. A 64-lead LQFP package is pin compatible with the ADV7181C.The 48-Lead LQFP, 40-lead LFCSP, and 32-lead LFCSP use one pin to output VS or FIELD.APPLICATIONS Digital camcorders and PDAs Low cost SDTV PIP decoder for digital TVs Multichannel DVRs for video security AV receivers and video transcoding PCI-/USB-based video capture and TV tuner cards Personal media players and recorders Smartphone/multimedia handsets In-car/automotive infotainment units Rearview camera/vehicle safety systems

The ADV7180 automatically detects and converts standard analog baseband television signals compatible with worldwide NTSC, PAL, and SECAM standards into 4:2:2 component video data compatible with the 8-bit ITU-R BT.656 interface standard.The simple digital output interface connects gluelessly to a wide range of MPEG encoders, codecs, mobile video processors, and Analog Devices, Inc., digital video encoders, such as the ADV7391. External HS, VS, and FIELD signals provide timing references for LCD controllers and other video ASICs, if required. Accurate 10-bit analog-to-digital conversion provides professional quality video performance for consumer applications with true 8-bit data resolution. Three analog video input channels accept standard composite, S-video, or component video signals, supporting a wide range of consumer video sources. AGC and clamp-restore circuitry allow an input video signal peak-to-peak range to 1.0 V. Alternatively, these can be bypassed for manual settings.The line-locked clock output allows the output data rate, timing signals, and output clock signals to be synchronous, asynchronous, or line locked even with ?5% line length variation. Output control signals allow glueless interface connections in many applications. The ADV7180 is programmed via a 2-wire, serial bidirectional port (I2C? compatible) and is fabricated in a 1.8 V CMOS process. Its monolithic CMOS construction ensures greater functionality with lower power dissipation. LFCSP package options makes the decoder ideal for space-constrained portable applications. A 64-lead LQFP package is pin compatible with the ADV7181C.The 48-Lead LQFP, 40-lead LFCSP, and 32-lead LFCSP use one pin to output VS or FIELD.APPLICATIONS Digital camcorders and PDAs Low cost SDTV PIP decoder for digital TVs Multichannel DVRs for video security AV receivers and video transcoding PCI-/USB-based video capture and TV tuner cards Personal media players and recorders Smartphone/multimedia handsets In-car/automotive infotainment units Rearview camera/vehicle safety systems

The ADV7390?/?ADV7391?/?ADV7392?/ ADV7393?are a family of high speed, digital-to-analog video encoders on single monolithic chips. Three 2.7 V/3.3 V, 10-bit video DACs (a single DAC for the WLCSP package) provide support for composite (CVBS), S-Video (Y-C), or component (YPrPb/RGB) analog outputs in either standard definition (SD) or high definition (HD) video formats. The single DAC WLCSP package supports CVBS (NTSC and PAL) output only in SD resolution (see Table 2).Optimized for low power operation, occupying a minimal footprint, and requiring few external components, these encoders are ideally suited to portable and power-sensitive applications requiring TV-out functionality. Cable detection and DAC auto power-down features ensure that power consumption is kept to a minimum.The ADV7390 / ADV7391 have an 8-bit video input port that supports SD video formats over an SDR interface and HD video formats over a DDR interface. The ADV7392 / ADV7393 have a 16-bit video input port that can be configured in a variety of ways. SD RGB input is supported.All members of the family support embedded EAV/SAV timing codes, external video synchronization signals, and the I2C? and communication protocol. Table 1 and Table 2 list the video standards directly supported by the ADV7390/ADV7391/ ADV7392/ADV7393 family.APPLICATIONS Mobile handsets Digital still cameras Portable media and DVD players Portable game consoles Digital camcorders Set-top box (STB) Automotive infotainment (ADV7392 and ADV7393 only)

The ADV7614 is a high quality, single-chip integrated 4:1 multiplexed High-Definition Multimedia Interface (HDMI?) receiver. The ADV7614 incorporates a quad input HDMI receiver that supports all HDTV formats up to 1080p and displays resolutions up to UXGA (1600 ? 1200 at 60 Hz). The reception of encrypted video is possible with the inclusion of HDCP. The HDMI receiver also includes programmable/adaptive equalization that ensures robust operation of the interface with cable lengths up to 30 meters.The ADV7614 provides complete audio support for eight channels of I2S audio, Sony/Philips digital interface format (S/PDIF) digital audio output, and super audio CD (SACD) and compressed SACD support with direct stream digital (DSD) and direct stream transfer (DST) output interfaces, respectively.The HDMI receiver also supports high bit rate (HBR) audio streaming to allow recovery (and downstream processing) of compressed lossless audio formats, including Dolby? TrueHD and DTS?-HD master audio or DTS-HD high resolution audio. In addition, it also provides an advanced audio functionality, such as a mute controller that prevents audible extraneous noise in the audio output.Fabricated in an advanced CMOS process, the ADV7614 is provided in a space-saving, 260-ball, 15 mm ? 15 mm, CSP_BGA surface-mount, RoHS-compliant package, and is specified over the ?40?C to +70?C temperature range. APPLICATIONS Advanced TVs AVR video receivers PDP HDTVs LCD TVs (HDTV ready) OLED HDTVs LCD/DLP front projectors HDMI switcher

The ADV7625 is a high performance, five-input, dual-output, High-Definition Multimedia Interface (HDMI?) transceiver with crosspoint and splitter capabilities. The ADV7625 supports 3 GHz video and features two independent HDMI receivers, two independent HDMI transmitters, two audio output ports, two audio input ports, and a pixel port input. The ADV7625 supports all HDCP repeater functions through fully tested Analog Devices, Inc., repeater software libraries and drivers.The HDMI receivers and transmitters in the ADV7625 support the reception and transmission of 3 GHz video formats up to 4k ? 2k at 24 Hz/25 Hz/30 Hz, in addition to all mandatory HDMI 3D TV formats. The receivers and transmitters also provide support for THX? Media Director?.Each HDMI receiver features an integrated equalizer that ensures robust operation of the interface with cable lengths up to 30 meters. The HDMI receivers share a 768-byte volatile extended display identification data (EDID) memory, which can facilitate one or two EDIDs, one for each receiver. Each HDMI port features dedicated 5 V detect and Hot Plug? assert pins.Each HDMI transmitter supports audio return channel (ARC) and features an integrated HDMI CEC controller that supports capability discovery and control (CDC).The ADV7625 offers two audio output ports and two audio input ports. Each audio port supports the extraction and insertion of up to eight channels of audio data out of or into the HDMI streams. HDMI audio formats, including I2S, S/PDIF, direct stream digital (DSD), and high bit rate (HBR) audio are supported.The ADV7625 features a TTL pixel port input that facilitates the reception of digital video data from an analog front-end decoder (for example, the ADV7180, ADV7181D, or ADV7842).The ADV7625 has an integrated on-screen display (OSD) generator that enables the creation and control of high quality character- and icon-based system status and control displays. The OSD can be overlaid on 3 GHz video formats and 3D video. Customers who are interested in using OSD are provided with Blimp, the Analog Devices OSD development tool.The ADV7625 is provided in a space-saving, 260-ball, 15 mm ? 15 mm CSP_BGA surface-mount, RoHS-compliant package and is specified over the 0?C to 70?C temperature range. APPLICATIONS AVRs Soundbar with HDMI repeater support Matrix switch Other repeater applications

The ADV7840 is a high quality, single chip, multiformat video decoder graphics digitizer with an integrated 4:1 multiplexed HDMI? receiver.This multiformat 3D comb filter decoder supports the conversion of PAL, NTSC, and SECAM standards in the form of a compositeor an S-Video input signal into a digital ITU-R BT.656 format.SCART and overlay functionality are enabled by the ability of theADV7840 to process CVBS and standard definition RGB signals simultaneously.The ADV7840 contains one main component processor (CP),which processes YPrPb and RGB component formats, including RGB graphics. The CP also processes the video signals from theHDMI receiver. The ADV7840 can operate in quad HDMI andanalog input mode, thus allowing for fast switching between theADCs and HDMI.The ADV7840 supports the decoding of a component RGB/YPrPb video signal into a digital YCrCb or RGB pixel output stream. The support for component video includes 525i, 625i,525p, 625p, 720p, 1080i, 1080p, and 1250i standards, as well asmany other HD and SMPTE standards.Graphics digitization is also supported by the ADV7840. TheADV7840 is capable of digitizing RGB graphics signals from VGA to UXGA rates and converting them into a digital RGB or YCrCb pixel output stream.The ADV7840 incorporates a quad input HDMI 1.3-compatible receiver that supports all HDTV formats up to 1080p and display resolutions up to UXGA (1600 ? 1200 at 60 Hz). The reception of encrypted video is possible with the inclusion of HDCP. The HDMI receiver also includes programmable equalization that ensures robust operation of the interface with cablelengths up to 30 meters. The HDMI receiver has advanced audio functionality, such as a mute controller, that prevents audible extraneous noise in the audio output.Fabricated in an advanced CMOS process, the ADV7840 is provided in a 19 mm ? 19 mm, 416-ball, CSP_BGA, surface-mount, RoHS-compliant package and is specified over the 0?C to +70?C temperature range.ApplicationsAdvanced TVsPDP HDTVsLCD TVs (HDTV ready)LCD/DLP? rear projection HDTVsCRT HDTVsLCoS? HDTVsAVR video receiversLCD/DLP front projectorsHDTV STBs with PVRCRT HDTVProjectorsDVD recorders with progressive scan input support

The ADV8003 is a multiple input video signal processor that can de-interlace and scale SD, ED, or HD video data to HD formats, generate a bitmap on-screen display (OSD) and output the video with OSD overlaid on two High Definition Multimedia Interface (HDMI) transmitters and a video encoder.Video can be input into the ADV8003 in a number of ways: using the 48-bit TTL pixel port, using the 24-bit external OSD TTL pixel port, or from a device with a HDMI transmitter such as the ADV7850. The ADV8003 supports many of the formats outlined in the CEA-861 and VESA specifications, as well as several other widely used timing formats.Using two external DDR2 memories, the ADV8003 can perform high performance, motion adaptive interlaced to progressive conversion on SD and HD content. Using a single DDR2 memory, the HD de-interlacing is limited to intrafield.The ADV8003 features primary and secondary video scalers that enable simultaneous output of multiple different resolutions. Detail enhancement and image enhancing techniques such as random, mosquito, and block noise reduction allow for improved final image quality. The frame rate converter of the ADV8003 allows the conversion between common frame rates with support to output two different frame rates simultaneously under certain conditions.The ADV8003 has a flexible digital core that allows the user to configure the part in several different modes: using a single video processing channel, using dual video processing channels, or displaying OSD on multiple outputs of different resolutions. The ADV8003 can accept OSD information from either an external OSD source on the 24-bit external OSD TTL pixel data input or internally generate a high quality, bitmap-based OSD. The internal OSD is highly flexible and allows the system designer to easily incorporate features like scrolling text and animation in various color depths up to 24-bit true color.Analog Devices, Inc., provides an OSD development tool (Blimp) to assist in the design, debug, and emulation of the OSD prior to integration with the system application. When the design is complete, the OSD development tool automatically generates code to which system APIs can be added before integration with the system application and an OSD design resource, which must be downloaded to an external SPI flash memory.Video can be output from the ADV8003 using one or both of the HDMI transmitters and/or the 6-DAC SD/HD video encoder. The flexible multiplexing in the part allows simultaneous output of HD formats on the HDMI transmitters and on the HD DACs (for example, 1080p) with SD formats on the SD DACs (for example, 480i).Both of the HDMI transmitters on the ADV8003 support all mandatory and many optional 3D video resolutions and audio return channels (ARC). Each transmitter also features a full CEC master. The ADV8003 can receive up to six channels of I2S, S/PDIF, direct stream digital (DSD), and high bit rate (HBR). The six 12-bit NSV? video DACs allow for composite (CVBS), S-Video (Y/C), and component (YPrPb) analog outputs in standard, enhanced, and high definition video formats. Oversampling of 216 MHz (SD and ED) and 297 MHz (HD) removes the requirement for external output filtering.The ADV8003 can also support 30-bit TTL in and 30-bit TTL out mode for professional applications.The ADV8003 supports the I2C? protocol for communication with the system microcontroller.APPLICATIONS High end A/V receivers Upconverting DVD players/recorders Blu-ray players/recorders Set-top boxes Video conferencing Standalone video processors HDMI splitters

The ADXL1001/ADXL1002 deliver ultralow noise density over an extended frequency range with two full-scale range options, and are optimized for industrial condition monitoring. The ADXL1001 (?100 g) and the ADXL1002 (?50 g) have typical noise densities of 30 ?g/?Hz and 25 ?g/?Hz, respectively. Both accelerometer devices have stable and repeatable sensitivity, which is immune to external shocks up to 10,000 g.The ADXL1001/ADXL1002 have an integrated full electrostatic self test (ST) function and an overrange (OR) indicator that allow advanced system level features and are useful for embedded applications. With low power and single-supply operation of 3.3 V to 5.25 V, the ADXL1001/ADXL1002 also enable wireless sensing product design. The ADXL1001/ ADXL1002 are available in a 5 mm ? 5 mm ? 1.80 mm LFCSP package, and are rated for operation over a ?40?C to +125?C temperature range.Applications Condition monitoring Predictive maintenance Asset health Test and measurement Health usage monitoring system (HUMS)

The ADXL195?/ ADXL295 are dual spectrum accelerometers that measure baseband acceleration in up to two axes (XL-X and XL-Y), as well as high frequency (HF) acceleration energy. Identical, independent X and Y sense structures are implemented to achieve the best possible fail-safe performance.The XL-X and XL-Y channels output baseband acceleration information with a nominal full-scale range of ?120 g and a bandwidth of 408 Hz. The acceleration data is provided as a 12-bit, twos complement word with a resolution of 62.5 mg/LSB.HF acceleration within the frequency band of 15.5 kHz to 23 kHz is rectified and filtered to generate an average g (gAVG) energy measurement. The HF channel has a nominal full-scale range of 40 gAVG and a bandwidth of 393 Hz. When combined with the XL-X and XL-Y information, HF acceleration information allows for enhanced vehicle impact detection and discrimination.The ADXL195 / ADXL295 are available in a 16-lead, narrow-body SOIC package with an exposed pad. The ADXL195 / ADXL295 can operate at 3.3 V and 5 V and are specified for operation from ?40?C to +105?C.APPLICATIONS Enhanced crash sensing Shock detection