AN-1558 Clocking High-Speed A/D Converters (Rev. B)

Extremely high-speed ADCs (>1 GSPS) demand a low-jitter sample clock in order to preserve signal-tonoiseratio (SNR). These 8- and 10-bit converters have best-case noise floors set by quantization noise.For an N-bit ADC sampling a full-scale sinusoid the well known expression for SNR (in dB) is: SNR =6.02N + 1.76. This sets the best case noise floor for an 8-bit ADC at −49.9 dBc. The noise f