Optimizing JPEG on the TMS320C6211 2-Level Cache DSP

Texas Instruments

Published Date: 09/13/2000


This application report describes the implementation and optimization techniques of the Joint Photographic Experts Group (JPEG) the still image compression standard on the TMS320C6211. The TMS320C6211 is a low-cost and high-performance digital signal processor (DSP) with 2-level caches that utilizes the VelociTI? very-long-instruction-word (VLIW) architecture.The TMS320C6211 has 64KB of L2 m


Part Number Name Companion Part
TMS320C6211BGFN150 TMS320C6211BGFN150 Buy Datasheet
TMS320C6211BGFN167 TMS320C6211BGFN167 Buy Datasheet
TMS320C6211BGFN180 TMS320C6211BGFN180 Buy Datasheet
TMS320C6211BZFN150 TMS320C6211BZFN150 Buy Datasheet
TMS320C6211BZFN167 TMS320C6211BZFN167 Buy Datasheet
TMS32C6211BZFN180H TMS32C6211BZFN180H Buy Datasheet