This application report contains implementation instructions for the Serial Rapid I/O (SRIO) interface on the TMS320TCI6482 DSP device. The approach to specifying interface timing and physical requirements for the SRIO interface is quite different than previous approaches for other interfaces.

Serial Rapid I/O is an industry-standard high-speed switched-packet interconnect. Physical layer data

Comparison of COP878x to the Enhanced COP8SAx7 Family - Hardware/Software Considerati ons

This document describes the GSM adaptive multi-rate (AMR) voice coding implementation on the TMS320C62x(tm) generation DSP. It discusses the system requirements and provides two levels of detail for the subroutines--one for programmers who want to use the code in a basic GSM architecture and the other for programmers who want to use the code as a basis for optimizing code or modifying other algor

This application report describes the interface between the host port interface (HPI) and the external memory interface (EMIF) of the TMS320C6000™ digital signal processor (DSP). This report examines three possible pairings of the various TMS320C6000 devices: TMS320C6201/C6701 EMIF to TMS320C6201/C6701 HPI TMS320C6211C/C6711 EMIF to TMS320C6211/C6711 HPI and TMS320C64x™ EMIF to TMS3

This document describes the TRF2050 evaluation board and associated software. The TRF2050 evaluation board is comprised of a multi-layer printed circuit board. The following are included to aid in the assessment of this device:- The TRF2050 Functional Block Diagram- The TRF2050 Evaluation Board Mechanical Outline- The Evaluation Board Schematic- The Evaluation Board Part ListThe volt

The Texas Instruments (TI)(tm) TMS320 family of digital signal processors (DSPs) is widely used for digital image processing. Color space transformation one of the basic image processing algorithms is used for digital still camera color printer color scanner and other video product applications.This application report describes how to implement the algorithm of transforming the image color

Differential line receivers commonly have fail-safe circuits to prevent the receiver from switching on input noise. Many innovative LVDS fail-safe solutions require either external components, with su

PCIe 1.0a Device Prevent Resume from S1 Application Note

Using surface-mount packages double-sided boards and multi-chip modules in board design results in the loss of physical access to the signals on these boards. JTAG or boundary scan provides a means of testing printed circuit boards and modules that might otherwise be untestable. This documents is a brief introduction to TI JTAG and its documentation. The basics of boundary scan are discussed.

This application note discusses how phase synchronization can be achieved when multiple chips are involved and also when the frequencies are not the same.

Recently, there has been a big demand for connectivity in the consumer's and industrial's applications. The requirements and implementations are different, but the common denominator is reliability, r

This application report describes an interface between the Motorola MPC860 microprocessor and the host port interface (HPI) of a Texas Instruments TMS320C6000™ (C6000™) digital signal processor (DSP) device. This document includes a schematic showing connections between the two devices PAL equations and verification that timing requirements are met for each device (tables and timing

This application report and associated code files provide functionality for copying initialized compiler sections from the internal Flash memory to the internal random access memory (RAM) of the TMS32

Reference Design TPS659119-Q1

ADS8363, ADS7863, ADS7223 Interfacing to the ADS8363 Pseudo-Differential Operating Mode

The TAS5132EVM PurePath Digital™ customer evaluation module (EVM) demonstrates the integrated circuits TAS5086PAG and TAS5132DDV from Texas Instruments. This application report covers the EVM specifications audio performance and power efficiency measurements graphs and design documentation that includes schematics parts list layout and mechanical design.

The Single-Ended Primary Inductance Converter (SEPIC) can convert an input voltage to an output voltage that is higher, lower, or equal to the input. Conversion is performed without the use of expensi

ADS6129, ADS6149 Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat

TAS5066-5112F6EVM Application Report

Placing code and constant data in ROM can lead to a big benefit in system cost. Since ROM area is typically one quarter the size of equivalent RAM the DSP silicon cost is lower. Performance is also improved since accessing ROM is faster than accessing external memory.

There are however software considerations when ROMing components. For example 'C6000 direct accesses to .bss global variab