This application report describes methods to interface TPS57xxx-Q1, TPS65320-Q1 Family, and TPS65321-Q1 devices to an external system clock. It proposes a new AC-coupled interface circuit avoiding any DC-bias conditions on the RT/CLK pin. This document also discusses important design details and provides optimizations of existing clock-interface circuits.
The device can support VI voltages up to 4.8 V. While the AVDD and ELVSS converter do not change their operation modes for VI > 4.5 V the ELVDD boost converter operates in “Diode-Mode” to support a lower output voltage than its input voltage.