| Distributor | SKU | Stock | Cost | |
|---|---|---|---|---|
| DigiKey | OP120 | 0 | Buy |
OP120 Dual QSFP28 FMC for 100G Networking on FPGA Development Boards
Opsero OP120 is an FPGA mezzanine card that adds two QSFP28 module slots to FPGA and SoC-based development boards. Each slot accepts QSFP, QSFP+, or QSFP28 optical or copper modules and provides four serial lanes of up to 25 Gbps per lane — an aggregate of 100 Gbps per port and 200 Gbps across both ports. This gives engineers working on 100G Ethernet, Interlaken, CPRI, and other high-speed serial protocols a compact and carrier-agnostic way to prototype and validate their designs.
The card connects to the carrier via a high pin count FMC connector conforming to the VITA 57.1 standard, routing all eight high-speed lanes to the carrier FPGA's gigabit transceivers. An on-board jitter-attenuating clock multiplier supports recovered clock operation and Synchronous Ethernet (SyncE), making the OP120 suitable for timing-sensitive network designs as well as pure throughput workloads. Reference clocks can be sourced from the FPGA, from a recovered data stream, or from an on-board oscillator.
Level translators on the low-speed control signals allow the card to operate with FPGA I/O voltages from 1.2 V to 3.3 V, and test points are provided on key signals to simplify bring-up and debugging. The OP120 ships with example designs and full sources for multiple development boards, including both standalone and PetaLinux builds. These reference designs cover multi-gigabit Ethernet bring-up and give engineers a working starting point, reducing the effort required to go from an FMC installation to a validated data plane.