Description

The purpose of this application note is to help FPGA designers to implement the Triple Module Redundancy (TMR) design technique on a VHDL design, which is targeted on a Microchip Radiation-Tolerant PolarFire (RT PolarFire) FPGA.

This application note describes how to implement each logical register with a TMR register on different hierarchies of a VHDL/Verilog design. It shows how to use the syn_radhardlevel synthesis attribute on the architecture and signal on different hierarchies.

These design example projects are targeted towards use in a RTPF500T-CG1509M device (Rad-Tolerant PolarFire FPGA, 500K Logic-Elements with High-Speed Serial Transceivers in a Ceramic Column Grid Array Package with 1509 solder columns).