Description

Up to 1GHz Dual-SHARC+ DSP with 2x 640KB L1, 2048KB Shared L2 SRAM, 400-Ball FCBGA Features:SHARC+ Core Infrastructure 800 MHz (max) or 1 GHz (max) Core clock frequency 2x 640KB on-chip Level 1 (L1) SRAM memory (with parity) increases low latency performance 32-bit, 40-bit & 64-bit floating point support 32-bit fixed point Byte, short-word, word, long-word addressedMemory 2048 KB on-chip Level 2 (L2) SRAM with ECC protection - eliminates need for external memory in many use cases Level 3 (L3) interface optimized for low system power, providing 16-bit interface to DDR3 (supporting 1.35 V capable DDR3L devices)16-bit DDR/DDR3L Memory Controller 1.35V support for DDR3LAdvanced Hardware Accelerators Enhanced FIR/IIR offload engines running at Core clock frequency for added processing power Security Crypto Engines with OTPPowerful DMA SystemInnovative Digital Audio Interface (DAI) includes: 8x Full SPORT interfaces w/TDM & I2S modes 2x S/PDIF Rx/Tx, 8 ASRC pairs 8x Precision Clock Generators 2x 4-channel PDM Mic Inputs 28 BuffersOther Peripheral Connectivity / Interfaces: 2x Quad SPI, 1x Octal SPI MLB 3-pin 6x I2C,3x UARTs 2x Link Ports 16x General Purpose Timer, 1x General Purpose Counter 3x Watchdog Timers 4-ch 12bit Housekeeping ADC 40 GPIO pins, 28 DAI pins Thermal SensorPackage 17mm x 17mm (0.8mm pitch) 400-ball FCBGA Fully pin-compatible with ADSP-21569, ADSP-21567, and ADSP-21566 processorsAdditional Features Security and Protection Crypto hardware accelerators Fast secure boot with IP protection Enhanced FIR and IIR accelerators running up to 1 GHz AEC-Q100 qualified for automotive applications