Description

Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs Features:Fully integrated dual VCO/PLL cores167 fs rms jitter from 0.637 MHz to 10 MHz at 106.25 MHz178 fs rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz418 fs rms jitter from 12 kHz to 20 MHz at 125 MHzInput crystal or clock frequency of 25 MHzPreset divide ratios for 106.25 MHz, 156.25 MHz, 33.33 MHz,100 MHz, 125 MHzChoice of LVPECL or LVDS output formatIntegrated loop filtersCopy of reference clock outputRates configured via strapping pinsSpace saving, 6 mm 6 mm, 40-lead LFCSP0.71 W power dissipation (LVDS operation)1.07 W power dissipation (LVPECL operation)3.3 V operation