Description

14-Output Clock Generator Features: Four 800 MHz LVDS outputs, arranged in 2 groups Each group has 2 cascaded 1-to-32 dividers with coarse phase delay Additive output jitter: 275 fs rms Fine delay adjust (Δt) on each LVDS output Each LVDS output can be reconfigured as two 250 MHz CMOS outputs  Six 1.6 GHz LVPECL outputs, arranged in 3 groups Each group shares a 1-to-32 divider with coarse phase delay Additive output jitter: 225 fs rms Channel-to-channel skew paired outputs of <10 ps See datasheet for additional features