Description

CMOS, 3V/5V, 500 A, 24-Bit Sigma-Delta, Signal Conditioning ADC Features: Charge Balancing ADC 24 Bits No Missing Codes 0.0015% Nonlinearity Five-Channel Programmable Gain Front End Gains from 1 to 128 Can Be Configured as Three Fully Differential Inputs or Five Pseudo-Differential Inputs Three-Wire Serial Interface SPI®, QSPI™, MICROWIRE™ and DSP Compatible 3 V (AD7714-3) or 5 V (AD7714-5) Operation Low Current (350 µA typ) with Power-Down (5 µA typ) Low Noise (<150 nV rms) Low-Pass Filter with Programmable Filter Cutoffs Please see data sheet for additional features