ADC, Successive Approximation, 14-Bit, 1 Func, 4 Channel, Parallel, Word Access, CMOS, PDSO28

Differential/Single-Ended Input, Dual, Simultaneous Sampling, 2 MSPS, 12-Bit, 3-Channel SAR A/D Converter Features: Dual 12-bit, 3-channel ADC Throughput rate: 2 MSPS Specified for VDD of 2.7 V to 5.25 V Power consumption: 9 mW at 1.5 MSPS with 3 V supplies 27 mW at 2 MSPS with 5 V supplies Pin-configurable analog inputs 12-channel single-ended inputs 6-channel fully differential inputs 6-channel pseudo differential inputs 70 dB SNR at 50 kHz input frequency Accurate on-chip reference: 2.5 V ±0.2% maximum @ 25°C, 20 ppm/°C maximum Dual conversion with read 437.5 ns, 32 MHz SCLK High speed serial interface SPI®-/QSPI™-/MICROWIRE&trade-/DSP-compatible −40°C to +125°C operation Shutdown mode: 1 μA maximum 32-lead LFCSP and 32-lead TQFP 1 MSPS version, AD7265

CMOS Low Voltage 2 SPST Switches

SPST, 1 Func, 1 Channel, CMOS, PDSO5

Differential Input, Dual, Simultaneous Sampling, 5 MSPS, 12-Bit, SAR ADC Features: Dual 12-bit SAR ADC Simultaneous Sampling Throughput rate: 5 MSPS per channel Specified for VDD at 2.5 V No conversion latency Power dissipation: 36 mW at 5 MSPS On-chip reference: 2.048 V ± 0.25%, 6ppm/°C Dual conversion with read High speed serial interface: SPI-/QSPI™-/MICROWIRE™-/DSP-compatible −40°C to +125°C operation Available in a 16-lead TSSOP

10-Bit, 4 Oversampling SDTV Video Decoder Features: Automotive versions qualified per AEC-Q100, Grade 1 Worldwide NTSC/PAL/SECAM color demodulation support One 10-bit ADC, 4× oversampling for CVBS, 2× oversampling for Y/C mode, and 2× oversampling for YPrPb (per channel) 3 video input channels with on-chip antialiasing filter CVBS (composite), Y/C (S-video), and YPrPb (component) video input support 5-line adaptive comb filters and CTI/DNR video enhancement Adaptive Digital Line Length Tracking (ADLLT), signal processing, and enhanced FIFO management give mini-TBC functionality See data sheet for additional features

3-Axis, 2 g/4 g/8 g/16 g Digital Accelerometer

Low Noise, Low Input Bias Current, Rail-to-Rail Output, JFET Dual Operational Amplifier

Low Voltage Controller for Touch Screens Features: 4-wire touch screen interface 1.6 V to 3.6 V operation Median and averaging filter to reduce noise Automatic conversion sequencer and timer User-programmable conversion parameters Auxiliary analog input/battery monitor (0.5 V to 5 V) 1 optional GPIO Interrupt outputs (INT, PENIRQ) Touch-pressure measurement Wake-up on touch function Shutdown mode: 6 μA maximum 12-ball, 1.6 mm × 2 mm WLCSP 16-lead, 4 mm × 4 mm LFCSP

0.28 CMOS 1.65 V to 3.6 V Single SPST Switches in SC70

1.6 V, Micropower 12-/10-/8-Bit ADCs

1.6 V, Micropower 12-/10-/8-Bit ADCs

1.6 V, Micropower 12-/10-/8-Bit ADCs

1.6 V, Micropower 12-/10-/8-Bit ADCs

20 V, 500 mA, Low Noise, CMOS LDO Features: Input voltage range: 3.3 V to 20 V Maximum output current: 500 mA Low Noise: 15 μV rms for fixed output versions PSRR Performance of 60 dB at 10 kHz, VOUT = 3.3 V Reverse current protection Low dropout voltage: 350 mV at 500 mA Initial accuracy: ±0.8% Accuracy over line, load, and temperature −2% to +1%, TJ = −40°C to +125°C −1.25% to +1%, TJ = 0°C to +85°C Low quiescent current (VIN = 5 V), IGND = 900 μA with 500 mA load Low shutdown current: <40 μA at VIN = 12 V, stable with small 1 μF ceramic output capacitor 7 fixed output voltage options: 1.5 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 5 V, and 9 V Adjustable output from 1.22 V to VIN − VDO Foldback current limit and thermal overload protection User programmable precision UVLO/enable Power-good indicator 8-lead LFCSP and 8-lead SOIC packages

4 RON, 4-/8-Channel 15 V/+12 V/5 V iCMOS Multiplexers

Audio Subsystem with Class-D Speaker and Capless Headphone Driver

Synchronous Buck Controller with Constant On Time and Valley Current Mode

X-Stream 4.25 Gbps 40 40 Digital Crosspoint Switch Features: DC to 4.25 Gbps per port NRZ data rate Adjustable receive equalization 3 dB, 6 dB, or 12 dB boost Compensates over 40 inches of FR4 at 4.25 Gbps Adjustable transmit preemphasis/deemphasis Programmable boost and output level Compensates over 40 inches of FR4 at 4.25 Gbps Low Power 105 mW per channel at 2.5 V (400 mVP-P differential output level swing) 40 × 40, fully differential, nonblocking array Double rank connection programming with dual maps Low jitter, typically <25 ps Flexible 2.5 V to 3.3 V supply range DC- or ac-coupled differential PECL/CML inputs Differential CML outputs Per-lane polarity inversion for routing ease 50 Ω on-chip I/O termination with disable feature Supports 8b10b, scrambled or uncoded NRZ data Serial (I2C slave or SPI) control interface Parallel control interface

Cascadable IF VGAs with Programmable RMS Detectors