The AD5124/AD5144/AD5144A potentiometers provide a nonvolatile solution for 128-/256-position adjustment applications, offering guaranteed low resistor tolerance errors of ±8% and up to ±6 mA current density in the Ax, Bx, and Wx pins.The low resistor tolerance and low nominal temperature coefficientsimplify open-loop applications as well as applications requiringtolerance matching.The linear gain setting mode allows independent programmingof the resistance between the digital potentiometer terminals, through the RAW and RWB string resistors, allowing very accurate resistor matching.The high bandwidth and low total harmonic distortion (THD)ensure optimal performance for ac signals, making these devicessuitable for filter design.The low wiper resistance of only 40 Ω at the ends of the resistor array allow for pin-to-pin connection.The wiper values can be set through an SPI-/I2C-compatible digital interface that is also used to read back the wiper register andEEPROM contents.The AD5124/AD5144/AD5144A are available in a compact, 24-lead, 4 mm × 4 mm LFCSP and a 20-lead TSSOP. The partsare guaranteed to operate over the extended industrial temperaturerange of −40°C to +125°C.APPLICATIONS Portable electronics level adjustment LCD panel brightness and contrast controls Programmable filters, delays, and time constants Programmable power suppliesThe AD5144-EP supports defense and aerospace applications (AQEC).

The AD5124/AD5144/AD5144A potentiometers provide a nonvolatile solution for 128-/256-position adjustment applications, offering guaranteed low resistor tolerance errors of ±8% and up to ±6 mA current density in the Ax, Bx, and Wx pins.The low resistor tolerance and low nominal temperature coefficientsimplify open-loop applications as well as applications requiringtolerance matching.The linear gain setting mode allows independent programmingof the resistance between the digital potentiometer terminals, through the RAW and RWB string resistors, allowing very accurate resistor matching.The high bandwidth and low total harmonic distortion (THD)ensure optimal performance for ac signals, making these devicessuitable for filter design.The low wiper resistance of only 40 Ω at the ends of the resistor array allow for pin-to-pin connection.The wiper values can be set through an SPI-/I2C-compatible digital interface that is also used to read back the wiper register andEEPROM contents.The AD5124/AD5144/AD5144A are available in a compact, 24-lead, 4 mm × 4 mm LFCSP and a 20-lead TSSOP. The partsare guaranteed to operate over the extended industrial temperaturerange of −40°C to +125°C.APPLICATIONS Portable electronics level adjustment LCD panel brightness and contrast controls Programmable filters, delays, and time constants Programmable power suppliesThe AD5144-EP supports defense and aerospace applications (AQEC).

The AD5310R / AD5311R, members of the nanoDAC™ family, are low power, single-channel, 10-bit buffered voltage-out DACs. The devices include a 2.5 V, 2 ppm/°C internal reference. The output span can be programmed to be 0 V to VREF or 0 V to 2 × VREF. All devices operate from a single 2.7 V to 5.5 V supply and are guaranteed monotonic by design. The devices are available in 10-lead MSOP packages.The AD5310R / AD5311R also incorporate a power-on resetcircuit that ensures that the DAC output powers up to zeroscaleand remains there until a valid write takes place. Thedevice contains a power-down feature that reduces the currentconsumption of the device to 2 μA at 5 V while in power-downmode.The AD5310R / AD5311R use a versatile SPI or I2C interface,including an asynchronous RESET pin and a VLOGIC pin, allowing 1.8 V compatibility.PRODUCT HIGHLIGHTS High Relative Accuracy (INL): ±0.5 LSB maximum. Low Drift 2.5 V On-Chip Reference: 5 ppm/°C maximum temperature coefficient.APPLICATIONS Process controls Data acquisition systems Digital gain and offset adjustment Programmable voltage sources Optical modules

The AD5535B is a 32-channel, 14-bit denseDAC® with an on-chip high voltage output amplifier. This device is targeted for optical micro-electromechanical systems. The output voltage range is programmable via the REF_IN pin. The output range is 0 V to 50 V when REF_IN = 1 V, and 0 V to 200 V when REF_IN = 4 V. Each amplifier can source 550 μA, which is ideal for the deflection and control of optical MEMS mirrors.The selected digital-to-analog converter (DAC) register is written to via the 3-wire interface. The serial interface operates at clock rates of up to 30 MHz and is compatible with DSP and micro-controller interface standards.The device is operated with AVCC = 4.75 V to 5.25 V, DVCC = 2.7 V to 5.25 V, V+ = 4.75 V to 5.25 V, and VPP of up to 225 V. REF_IN is buffered internally on the AD5535B and should be driven from a stable reference source.Applications Optical microelectromechanical systems (MEMS) Optical crosspoint switches Micropositioning applications using piezoelectric actuators Level setting in automotive test and measurement

The AD5683R/AD5682R/AD5681R/AD5683, members of thenanoDAC+® family, are low power, single-channel, 16-/14-/12-bitbuffered voltage out digital-to-analog converters (DACs). Thedevices, except the AD5683, include an enabled by default internal2.5 V reference, offering 2 ppm/°C drift. The output span can beprogrammed to be 0 V to VREF or 0 V to 2 × VREF. All devicesoperate from a single 2.7 V to 5.5 V supply and are guaranteedmonotonic by design. The devices are available in a 2.00 mm ×2.00 mm, 8-lead LFCSP or a 10-lead MSOP.The internal power-on reset circuit ensures that the DAC registeris written to zero scale at power-up while the internal outputbuffer is configured in normal mode. TheAD5683R/AD5682R/AD5681R/AD5683 contain a power-downmode that reduces the current consumption of the device to 2 µA(maximum) at 5 V and provides software selectable output loadswhile in power-down mode.The AD5683R/AD5682R/AD5681R/AD5683 use a versatile3-wire serial interface that operates at clock rates of up to 50 MHz.Some devices also include asynchronous RESET pin and VLOGICpin options, allowing 1.8 V compatibilityProduct Highlights High Relative Accuracy (INL). AD5683R/AD5683 (16-bit): ±2 LSB maximum. Low Drift, 2.5 V On-Chip Reference. 2 ppm/°C typical temperature coefficient. 5 ppm/°C maximum temperature coefficient. Two Package Options. 2.00 mm × 2.00 mm, 8-lead LFCSP. 10-lead MSOP.Applications Process controls Data acquisition systems Digital gain and offset adjustment Programmable voltage sources

The AD5684, a member of the nanoDAC+™ family, is a low power, quad, 12-bit buffered voltage output DAC. The device includes a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The device operates from a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design, and exhibits less than 0.1% FSR gain error and 1.5 mV offset error performance. The device is available in a 3 mm × 3 mm LFCSP and a TSSOP package.The AD5684 also incorporates a power-on reset circuit and a RSTSEL pin that ensures that the DAC outputs power up to zero scale or midscale and remain at that level until a valid write takes place. Each part contains a per-channel power-down feature that reduces the current consumption of the device to 4 μA at 3 V while in power-down mode.The AD5684 employs a versatile SPI interface that operates at clock rates up to 50 MHz, and all devices contain a VLOGIC pin intended for 1.8 V/3 V/5 V logic.Product Highlights High Relative Accuracy (INL): ±1 LSB maximum Excellent DC Performance. Total unadjusted error: ±0.1% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.1% of FSR maximum Two Package Options: 3 mm × 3 mm, 16-lead LFCSP and 16-lead TSSOPApplications Digital gain and offset adjustment Programmable attenuators Process control (PLC I/O cards) Industrial automation Data acquisition systems

The AD5684R nanoDAC+™ is a quad, 12-bit, rail-to-rail, voltage output DAC. The device includes a 2.5V, 2ppm/˚C internal reference (enabled by default) and a gain select pin giving a full-scale output of 2.5V (gain=1) or 5V (gain=2). The device operates from a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design and exhibits less than 0.1% FSR gain error and 1.5mV offset error performance. The device is available in a 3mm X 3mm LFCSP and a TSSOP package.The AD5684R also incorporates a power-on-reset circuit and a RSTSEL pin that ensures the DAC outputs power up to zero-scale or midscale, and remain there until a valid write takes place. Each device contains a per-channel power-down feature that reduces the current consumption of the device to 4 uA at 3 V while in power-down mode.The AD5684R employs a versatile SPI interface that operates at clock rates up to 50 MHz and includes a VLOGIC pin intended for 1.8V/3V/5V logic.Product Highlights High relative accuracy: AD5684R (12-bit): ±1LSB INL max Low drift on-chip reference: 2.5V, 2ppm/°C temperature drift Two package options: 3mm × 3mm 16-lead LFCSP or 16-lead TSSOPApplications Optical transceivers Base-station power amplifiers Process control (PLC I/O cards) Industrial automation Data acquisition systems

The AD5689R/AD5687R members of the nanoDAC+™ family are low power, dual, 16-/12-bit buffered voltage output digital-to-analog converters (DACs). The devices include a 2.5 V, 2 ppm/°C internal reference (enabled by default) and a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The devices operate from a single 2.7 V to 5.5 V supply, are guaranteed monotonic by design, and exhibit less than 0.1% FSR gain error and 1.5 mV offset error performance. Both devices are available in a 3 mm × 3 mm LFCSP and a TSSOP package.The AD5689R/AD5687R also incorporate a power-on reset circuit and a RSTSEL pin that ensure that the DAC outputs power up to zero scale or midscale and remain there until a valid write takes place. Each part contains a per channel power-down feature that reduces the current consumption of the device to 4 μA at 3 V while in power-down mode.The AD5689R/AD5687R use a versatile serial peripheral interface (SPI) that operates at clock rates up to 50 MHz. Both devices contain a VLOGIC pin that is intended for 1.8 V/3 V/5 V logic.Product Highlights High Relative Accuracy (INL). AD5689R (16-bit): ±2 LSB maximum AD5687R (12-bit): ±1 LSB maximum Low Drift 2.5 V On-Chip Reference.  2 ppm/°C typical temperature coefficient  5 ppm/°C maximum temperature coefficient  Two Package Options.  3 mm × 3 mm, 16-lead LFCSP 16-lead TSSOP Applications Optical transceivers Base station power amplifiers Process control (PLC I/O cards) Industrial automation Data acquisition systems

The AD5695R is a low power, quad, 14-bit buffered voltage output DAC. The device includes a 2.5 V, 2 ppm/°C internal reference (enabled by default) and a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The device operates from a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design, and exhibits less than 0.1% FSR gain error and 1.5 mV offset error performance. The device is available in a 3 mm × 3 mm LFCSP and a TSSOP package.The AD5695R also incorporates a power-on reset circuit and a RSTSEL pin that ensures that the DAC outputs power up to zero scale or midscale and remain there until a valid write takes place. Each part contains a per-channel power-down feature that reduces the current consumption of the device to 4 μA at 3 V while in power-down mode.The AD5695R uses a versatile 2-wire serial interface that operates at clock rates up to 400 kHz, and includes a VLOGIC pin intended for 1.8 V/3 V/5 V logic.Product Highlights High Relative Accuracy (INL). AD5695R (14-bit): ±1 LSB maximum. Low Drift 2.5 V On-Chip Reference. 2 ppm/°C typical temperature coefficient. 5 ppm/°C maximum temperature coefficient. Two Package Options. 3 mm × 3 mm, 16-lead LFCSP. 16-lead TSSOP.Applications Optical transceivers Base-station power amplifiers Process control (PLC I/O cards) Industrial automation Data acquisition systems

The AD5696, a member of the nanoDAC+™ family, is a low power, quad, 16-bit buffered voltage output DAC. The device includes a gain select pin giving a full-scale output of 0V to VREF (gain = 1) or 0V to 2VREF (gain = 2) The device operates from a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design, and exhibits less than 0.1% FSR gain error and 1.5 mV offset error performance. The device is available in a 3 mm × 3 mm LFCSP package and in a TSSOP package.The AD5696 incorporates a power-on reset circuit and a RSTSEL pin; the RSTSEL pin ensures that the DAC outputs power up to zero scale or midscale and remain at that level until a valid write takes place. The part contains a per-channel power-down feature that reduces the current consumption of the device in power-down mode to 4 µA at 3 V.The AD5696 uses a versatile 2-wire serial interface that operates at clock rates up to 400 kHz and includes a VLOGIC pin intended for 1.8 V/3 V/5 V logic.Product Hightlights High Relative Accuracy (INL): ±2 LSB maximum Excellent DC Performance: Total unadjusted error: ±0.1% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.1% of FSR maximum Two Package Options: 3 mm × 3 mm, 16-lead LFCSP and 16-lead TSSOPApplications Digital gain and offset adjustment Programmable attenuators Process control (PLC I/O cards) Industrial automation Data acquisition systems

The AD5696R is a low power, quad, 16-bit buffered voltage output DAC. The device includes a 2.5 V, 2 ppm/°C internal reference (enabled by default) and a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The device operates from a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design, and exhibits less than 0.1% FSR gain error and 1.5 mV offset error performance. The device is available in a 3 mm × 3 mm LFCSP and a TSSOP package.The AD5696R also incorporates a power-on reset circuit and a RSTSEL pin that ensures that the DAC outputs power up to zero scale or midscale and remain there until a valid write takes place. Each part contains a per-channel power-down feature that reduces the current consumption of the device to 4 μA at 3 V while in power-down mode.The AD5696R uses a versatile 2-wire serial interface that operates at clock rates up to 400 kHz, and includes a VLOGIC pin intended for 1.8 V/3 V/5 V logic.Product Highlights High Relative Accuracy (INL). AD5696R (16-bit): ±2 LSB maximum. Low Drift 2.5 V On-Chip Reference. 2 ppm/°C typical temperature coefficient. 5 ppm/°C maximum temperature coefficient. Two Package Options. 3 mm × 3 mm, 16-lead LFCSP. 16-lead TSSOP.Applications Optical transceivers Base-station power amplifiers Process control (PLC I/O cards) Industrial automation Data acquisition systems

The AD5696R is a low power, quad, 16-bit buffered voltage output DAC. The device includes a 2.5 V, 2 ppm/°C internal reference (enabled by default) and a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The device operates from a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design, and exhibits less than 0.1% FSR gain error and 1.5 mV offset error performance. The device is available in a 3 mm × 3 mm LFCSP and a TSSOP package.The AD5696R also incorporates a power-on reset circuit and a RSTSEL pin that ensures that the DAC outputs power up to zero scale or midscale and remain there until a valid write takes place. Each part contains a per-channel power-down feature that reduces the current consumption of the device to 4 μA at 3 V while in power-down mode.The AD5696R uses a versatile 2-wire serial interface that operates at clock rates up to 400 kHz, and includes a VLOGIC pin intended for 1.8 V/3 V/5 V logic.Product Highlights High Relative Accuracy (INL). AD5696R (16-bit): ±2 LSB maximum. Low Drift 2.5 V On-Chip Reference. 2 ppm/°C typical temperature coefficient. 5 ppm/°C maximum temperature coefficient. Two Package Options. 3 mm × 3 mm, 16-lead LFCSP. 16-lead TSSOP.Applications Optical transceivers Base-station power amplifiers Process control (PLC I/O cards) Industrial automation Data acquisition systems

The AD5696R is a low power, quad, 16-bit buffered voltage output DAC. The device includes a 2.5 V, 2 ppm/°C internal reference (enabled by default) and a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The device operates from a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design, and exhibits less than 0.1% FSR gain error and 1.5 mV offset error performance. The device is available in a 3 mm × 3 mm LFCSP and a TSSOP package.The AD5696R also incorporates a power-on reset circuit and a RSTSEL pin that ensures that the DAC outputs power up to zero scale or midscale and remain there until a valid write takes place. Each part contains a per-channel power-down feature that reduces the current consumption of the device to 4 μA at 3 V while in power-down mode.The AD5696R uses a versatile 2-wire serial interface that operates at clock rates up to 400 kHz, and includes a VLOGIC pin intended for 1.8 V/3 V/5 V logic.Product Highlights High Relative Accuracy (INL). AD5696R (16-bit): ±2 LSB maximum. Low Drift 2.5 V On-Chip Reference. 2 ppm/°C typical temperature coefficient. 5 ppm/°C maximum temperature coefficient. Two Package Options. 3 mm × 3 mm, 16-lead LFCSP. 16-lead TSSOP.Applications Optical transceivers Base-station power amplifiers Process control (PLC I/O cards) Industrial automation Data acquisition systems

The AD5696R is a low power, quad, 16-bit buffered voltage output DAC. The device includes a 2.5 V, 2 ppm/°C internal reference (enabled by default) and a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The device operates from a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design, and exhibits less than 0.1% FSR gain error and 1.5 mV offset error performance. The device is available in a 3 mm × 3 mm LFCSP and a TSSOP package.The AD5696R also incorporates a power-on reset circuit and a RSTSEL pin that ensures that the DAC outputs power up to zero scale or midscale and remain there until a valid write takes place. Each part contains a per-channel power-down feature that reduces the current consumption of the device to 4 μA at 3 V while in power-down mode.The AD5696R uses a versatile 2-wire serial interface that operates at clock rates up to 400 kHz, and includes a VLOGIC pin intended for 1.8 V/3 V/5 V logic.Product Highlights High Relative Accuracy (INL). AD5696R (16-bit): ±2 LSB maximum. Low Drift 2.5 V On-Chip Reference. 2 ppm/°C typical temperature coefficient. 5 ppm/°C maximum temperature coefficient. Two Package Options. 3 mm × 3 mm, 16-lead LFCSP. 16-lead TSSOP.Applications Optical transceivers Base-station power amplifiers Process control (PLC I/O cards) Industrial automation Data acquisition systems

The AD5700/AD5700-1 are single-chip solutions, designedand specified to operate as a HART® FSK half-duplex modem,complying with the HART physical layer requirements. TheAD5700/AD5700-1 integrate all of the necessary filtering, signaldetection, modulating, demodulating and signal generationfunctions, thus requiring few external components. The 0.5%precision internal oscillator on the AD5700-1 greatly reducesthe board space requirements, making it ideal for line-poweredapplications in both master and slave configurations. The maximumsupply current consumption is 115µA, making theAD5700/AD5700-1 an optimal choice for low power loop-powered applications.Transmit waveforms are phase continuous 1200 Hz and2200 Hz sinusoids. The AD5700/AD5700-1 contain accuratecarrier detect circuitry and use a standard UART interface.Applications Field transmitters HART multiplexers PLC and DCS analog I/O modules HART network connectivity

The AD6643 is an 11-bit, 200 MSPS/250 MSPS, dual-channel intermediate frequency (IF) receiver specifically designed to support multi-antenna systems in telecommunication applications where high dynamic range performance, low power, and small size are desired.The device consists of two high performance analog-to-digital converters (ADCs) and noise shaping requantizer (NSR) digital blocks. Each ADC consists of a multistage, differential pipelined architecture with integrated output error correction logic, and each ADC features a wide bandwidth switched capacitor sampling network within the first stage of the differential pipeline. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) compensates for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.Each ADC output is connected internally to an NSR block. The integrated NSR circuitry allows for improved SNR performance in a smaller frequency band within the Nyquist bandwidth. The device supports two different output modes selectable via the SPI. With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6643 supports enhanced SNR performance within a limited portion of the Nyquist bandwidth while maintaining an 11-bit output resolution.The NSR block can be programmed to provide a bandwidth of either 22% or 33% of the sample clock. For example, with a sample clock rate of 185 MSPS, the AD6643 can achieve up to 75.5 dBFS SNR for a 40 MHz bandwidth in the 22% mode and up to 73.7 dBFS SNR for a 60 MHz bandwidth in the 33% mode.When the NSR block is disabled, the ADC data is provided directly to the output at a resolution of 11 bits. The AD6643 can achieve up to 66.5 dBFS SNR for the entire Nyquist bandwidth when operated in this mode. This allows the AD6643 to be used in telecommunication applications such as a digital predistortion observation path where wider bandwidths are required.After digital signal processing, multiplexed output data is routed into an 11-bit output port such that the maximum data rate is 400 Mbps (DDR). These outputs are LVDS and support ANSI-644 levels.The AD6643 receiver digitizes a wide spectrum of IF frequencies. Each receiver is designed for simultaneous reception of a separate antenna. This IF sampling architecture greatly reduces compo-nent cost and complexity compared with traditional analog techniques or less integrated digital methods.Flexible power-down options allow significant power savings. Programming for device setup and control is accomplished using a 3-wire SPI-compatible serial interface with numerous modes to support board level system testing.The AD6643 is available in a Pb-free, RoHS-compliant, 64-lead, 9 mm × 9 mm lead frame chip scale package (LFCSP_VQ) and is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent.Product Highlights Two ADCs are contained in a small, space-saving, 9 mm × 9 mm × 0.85 mm, 64-lead LFCSP package. Pin selectable noise shaping requantizer (NSR) function that allows for improved SNR within a reduced bandwidth of up to 60 MHz at 185 MSPS. LVDS digital output interface configured for low cost FPGA families. Operation from a single 1.8 V supply. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary or twos complement), NSR, power-down, test modes, and voltage reference mode. On-chip integer 1-to-8 input clock divider and multichip sync function to support a wide range of clocking schemes and multichannel subsystems.Applications Communications Diversity radio and smart antenna (MIMO) systems Multimode digital receivers (3G) WCDMA, LTE, CDMA2000 WiMAX, TD-SCDMA I/Q demodulation systems General-purpose software radios

The AD6649 is a mixed-signal intermediate frequency (IF) receiverconsisting of dual 14-bit, 250 MSPS ADCs and a wideband digitaldownconverter (DDC) and a bypass-able sample rate converter (SRC). The AD6649 is designed to support communications applications where low cost, small size, wide bandwidth and versatility are desired.The dual ADC core features a multistage, differential pipelinedarchitecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.ADC data outputs are internally connected directly to the digitaldownconverter (DDC) of the receiver. The digital receiver has two channels and provides processing flexibility. Each receive channel has four cascaded signal processing stages: a 32-bit frequency translator (numerically controlled oscillator (NCO), an optional sample rate converter, a fixed FIR filter, and an fs/4 fixed-frequency NCO.In addition to the receiver DDC, the AD6649 has several functions that simplify the automatic gain control (AGC) function in the system receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.After digital processing, data is routed directly to the 14-bit output port. These outputs operate at 1.8 V LVDS signal levels.The AD6649 receiver digitizes a wide spectrum of IF frequencies.Each receiver is designed for simultaneous reception of the main channel and the diversity channel. This IF sampling architecture greatly reduces component cost and complexity compared with traditional analog techniques or less integrated digital methods. In diversity applications the output data format is real due to the final NCO which shifts the output center frequency to fs/4.Flexible power-down options allow significant power savings,when desired.Programming for setup and control is accomplished using a 3-pinSPI-compatible serial interface.The AD6649 is available in a 64-lead LFCSP and is specified overthe industrial temperature range of −40°C to +85°C.APPLICATIONS Communications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTE General-purpose software radios Broadband data applicationsPRODUCT HIGHLIGHTS Integrated dual, 14-bit, 250 MSPS ADC. Integrated wideband decimation filter and 32-bit complex NCO. Fast overrange and threshold detect. Proprietary differential input maintains excellent SNR performance for input frequencies up to 300 MHz. SYNC input allows synchronization of multiple devices. 3-pin, 1.8V SPI port for register programming and register readback.

The AD6673 is an 11-bit, 250 MSPS, dual-channel intermediate frequency (IF) receiver specifically designed to support multi-antenna systems in telecommunication applications where high dynamic range performance, low power, and small size are desired.The device consists of two high performance analog-to-digital converters (ADCs) and noise shaping requantizer (NSR) digital blocks. Each ADC consists of a multistage, differential pipelined architecture with integrated output error correction logic, and each ADC features a wide bandwidth switched capacitor sampling network within the first stage of the differential pipeline. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) compensates for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.Each ADC output is connected internally to an NSR block. The integrated NSR circuitry allows for improved SNR performance in a smaller frequency band within the Nyquist bandwidth. The device supports two different output modes selectable via the SPI. With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6673 supports enhanced SNR performance within a limited portion of the Nyquist bandwidth while maintaining an 11-bit output resolution.The NSR block can be programmed to provide a bandwidth of either 22% or 33% of the sample clock. For example, with a sample clock rate of 250 MSPS, the AD6673 can achieve up to 76.3 dBFS SNR for a 55 MHz bandwidth in the 22% mode and up to 73.5 dBFS SNR for a 82 MHz bandwidth in the 33% mode.When the NSR block is disabled, the ADC data is provided directly to the output at a resolution of 11 bits. The AD6673 can achieve up to 65.9 dBFS SNR for the entire Nyquist bandwidth when operated in this mode. This allows the AD6673 to be used in telecommunication applications such as a digital predistortion observation path where wider bandwidths are required.By default the ADC output data is routed directly to the two external JESD204B serial output lanes. These outputs are at current mode logic (CML) voltage levels. Two modes are supported such that output coded data is either sent through one lane or two (L = 1; F = 4 or L = 2; F = 2). Single lane operation supports converter rates up to 125 MSPS. Synchronization input controls (SYNCINB± and SYSREF±) are provided.PRODUCT HIGHLIGHTS The configurable JESD204B output block with an integrated phase-locked loop (PLL) to support up to 5 Gbps per lane with up to two lanes. IF receiver includes two, 11-bit, 250 MSPS ADCs with programmable noise shaping requantizer (NSR) function that allows for improved SNR within a reduced bandwidth of 22% or 33% of the sample rate. Support for an optional RF clock input to ease system board design. Proprietary differential input maintains excellent SNR performance for input frequencies of up to 400 MHz. An on-chip integer, 1-to-8 input clock divider and SYNC input allows synchronization of multiple devices. Operation from a single 1.8 V power supply. Standard serial port interface (SPI) that supports various product features and functions, such as controlling the clock DCS, power-down, test modes, voltage reference mode, overrange fast detection, and serial output configuration.APPLICATIONS Communications Diversity radio and smart antenna (MIMO) systems Multimode digital receivers (3G) TD-SCDMA, WiMAX, WCDMA, CDMA2000, GSM, EDGE, LTE I/Q demodulation systems General-purpose software radios

The AD7091 is a 12-bit successive approximation register analog-to-digital converter (SAR ADC) that offers ultralow power consumption (typically 367 μA at 3 V and 1 MSPS) while achieving fast throughput rates (1 MSPS with a 50 MHz SCLK). The AD7091 operates from a single 2.09 V to 5.25 V power supply. The AD7091 also features an on-chip conversion clock and a high speed serial interface.The conversion process and data acquisition are controlled using a CONVST signal and an internal oscillator. The AD7091 has a serial interface that allows data to be read after the conversion while achieving a 1 MSPS throughput rate. The AD7091 uses advanced design and process techniques to achieve very low power dissipation at high throughput rates.The reference is derived internally from VDD. This design allows the widest dynamic input range to the ADC; that is, the analog input range for the AD7091 is from 0 V to VDD.PRODUCT HIGHLIGHTS Lowest power 12-bit SAR ADC available. High Throughput Rate with Ultralow Power Consumption. Flexible Power/Throughput Rate Management. Average power scales with the throughput rate. Power-down mode allows the average power consumption to be reduced when the device is not performing a conversion. Reference Derived from the Power Supply. Single Supply Operation. APPLICATIONS Battery-powered systems Handheld meters Medical instruments Mobile communications Instrumentation and control systems Data acquisition systems Optical sensors Diagnostic/monitoring functions Energy harvesting

The AD7091R-2 / AD7091R-4 / AD7091R-8 family is a multichannel12-bit, ultralow power, successive approximation analog-to-digitalconverter (ADC) that is available in two, four, or eightanalog input channel options. The AD7091R-2 / AD7091R-4 /AD7091R-8 operate from a single 2.7 V to 5.25 V power supplyand are capable of achieving a sampling rate of 1 MSPS.The AD7091R-2 / AD7091R-4 / AD7091R-8 family offers up to eightsingle-ended analog input channels with a channel sequencerthat allows a preprogrammed selection of channels to be convertedsequentially. The AD7091R-2 / AD7091R-4 / AD7091R-8 alsofeature an on-chip conversion clock, an on-chip accurate 2.5 Vreference, and a high speed serial interface.The AD7091R-2 / AD7091R-4 / AD7091R-8 have a serial portinterface (SPI) that allows data to be read after the conversionwhile achieving a 1 MSPS throughput rate. The conversion processand data acquisition are controlled using the CONVST pin.The AD7091R-2 / AD7091R-4 / AD7091R-8 use advanced designtechniques to achieve ultralow power dissipation at highthroughput rates. They also feature flexible power managementoptions. An on-chip configuration register allows the user to set updifferent operating conditions. These include power management,alert functionality, busy indication, channel sequencing, andgeneral-purpose output pins. The MUXOUT and ADCIN pinsallow signal conditioning of the multiplexer output prior toacquisition by the ADC.APPLICATIONS Battery powered systems Personal digital assistants Medical instruments Mobile communications Instrumentation and control systems Data acquisition systems Optical sensors Diagnostic/monitoring functions