385 MHz BW IF Diversity Receiver Features: JESD204B (Subclass 1) coded serial digital outputs In band SFDR = 83 dBFS at 340 MHz (750 MSPS) In band SNR = 66.7 dBFS at 340 MHz (750 MSPS) 1.4 W total power per channel at 750 MSPS (default settings) Noise density = −153 dBFS/Hz at 750 MSPS 1.25 V, 2.5 V, and 3.3 V dc supply operation Flexible input range AD6674-750 and AD6674-1000 1.46 V p-p to 1.94 V p-p (1.70 V p-p nominal) AD6674-500 1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal) 95 dB channel isolation/crosstalk Amplitude detect bits for efficient automatic gain control (AGC) implementation Noise shaping requantizer (NSR) option for main receiver function Variable dynamic range (VDR) option for digital predistortion (DPD) function 2 integrated wideband digital processors per channel 12-bit numerically controlled oscillator (NCO), up to 4 cascaded half-band filters Differential clock inputs Integer clock divide by 1, 2, 4, or 8 Energy saving power-down modes Flexible JESD204B lane configurations Small signal dither

385 MHz BW IF Diversity Receiver Features: JESD204B (Subclass 1) coded serial digital outputs In band SFDR = 83 dBFS at 340 MHz (750 MSPS) In band SNR = 66.7 dBFS at 340 MHz (750 MSPS) 1.4 W total power per channel at 750 MSPS (default settings) Noise density = −153 dBFS/Hz at 750 MSPS 1.25 V, 2.5 V, and 3.3 V dc supply operation Flexible input range AD6674-750 and AD6674-1000 1.46 V p-p to 1.94 V p-p (1.70 V p-p nominal) AD6674-500 1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal) 95 dB channel isolation/crosstalk Amplitude detect bits for efficient automatic gain control (AGC) implementation Noise shaping requantizer (NSR) option for main receiver function Variable dynamic range (VDR) option for digital predistortion (DPD) function 2 integrated wideband digital processors per channel 12-bit numerically controlled oscillator (NCO), up to 4 cascaded half-band filters Differential clock inputs Integer clock divide by 1, 2, 4, or 8 Energy saving power-down modes Flexible JESD204B lane configurations Small signal dither

Universal LVDT Signal Conditioner Features: Single Chip Solution, Contains Internal Oscillator and Voltage Reference No Adjustments Required Interfaces to Half-Bridge, 4-Wire LVDT DC Output Proportional to Position 20 Hz to 20 kHz Frequency Range Unipolar or Bipolar Output Will Also Decode AC Bridge Signals Outstanding Performance Linearity: 0.05% Output Voltage: ±11 V Gain Drift: 20 ppm/°C (typ) Offset Drift: 5 ppm/°C (typ)

4-Channel, I2C, Ultralow Power 12-Bit ADC in 20-Lead LFCSP/TSSOP Features: I2C-compatible serial interface supports standard and fast modes Ultralow power: 90 μW typical at 3 V in fast mode Specified for VDD of 2.7 V to 5.25 V On-chip accurate 2.5 V reference, 5 ppm/°C typical drift 4 single-ended analog input channels ALERT function BUSY function Autocycle mode Wide input bandwidth 68 dB signal-to-noise ratio (SNR) typical at input frequency of 1 kHz Flexible power/throughput rate management No pipeline delays Power-down mode 550 nA typical at VDD = 5.25 V 435 nA typical at VDD = 3 V 20-lead LFCSP and TSSOP packages Temperature range: −40°C to +125°C

1 MSPS, Ultralow Power, 12-Bit ADC in 10-Lead LFCSP and MSOP Features: Fast throughput rate of 1 MSPS Specified for VDD of 2.7 V to 5.25 V Logic voltage VDRIVE of 1.65 V to 5.25 V INL of ±1 LSB maximum Analog input range of 0 V to VREF Ultralow power 349 µA typical at 3 V and 1 MSPS 264 nA typical at 3 V in power-down mode Internal 2.5 V reference, ±4.5 ppm/°C typical drift Wide input bandwidth Flexible power/throughput rate management High speed serial interface SPI®/QSPI™/MICROWIRE™/DSP compatible BUSY indicator Power-down mode 10-lead, 3 mm × 2 mm LFCSP and 10-lead MSOP packages Temperature range of −40°C to +125°C

Monolithic Multiplying DAC Featuring Wide Dynamic Range Features: Dynamic Range: 88.5 dB Resolution: 0.375 dB On-Chip Data Latches +5 V Operation AD7111A Pin Compatible with AD7524 Low Power

+2.5V to 5.5V, 230A Dual Rail-to-Rail Voltage Output 12-Bit DAC with Byte-Load Parallel Interface in 20-lead TSSOP Features: Dual 12-Bit DAC in 20-Lead TSSOP Low Power: 300 µA @ 5 V, 230 µA @ 3 V Power-Down to 200 nA @ 5 V, 80 nA @ 3 V Guaranteed Monotonic by Design Power-On-Reset to Zero Volts Double-Buffered Input Logic Simultaneous Update of DAC Outputs via LDAC pin (active low) Asynchronous Clear Facility via CLR pin (active low) Low Power Parallel Data Interface Temperature Range: −40°C to 105°C

2.5 V to 5.5 V, Parallel Interface Octal Voltage Output 8-Bit D/A Converter Features: Low power operation: 1.4 mA (max) at 3.6 V Power-down to 120 nA at 3 V, 400 nA at 5 V Guaranteed monotonic by design over all codes Rail-to-rail output range: 0 V to VREF or 0 V to 2 × VREF Power-on reset to 0 V Simultaneous update of DAC outputs via LDAC pin Asynchronous CLR facility Readback Buffered/unbuffered reference inputs 20 ns WR time 38-lead TSSOP/6 mm × 6 mm 40-lead LFCSP packaging Temperature range: –40°C to +105°C

4-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference Features: Three power modes RMS noise Low power: 24 nV rms at 1.17 SPS, gain = 128 (255 μA typical) Mid power: 20 nV rms at 2.34 SPS, gain = 128 (355 μA typical) Full power: 23 nV rms at 9.4 SPS, gain = 128 (930 μA typical) Up to 22 noise free bits in all power modes (gain = 1) Output data rate Full power: 9.38 SPS to 19,200 SPS Mid power: 2.34 SPS to 4800 SPS Low power: 1.17 SPS to 2400 SPS Rail-to-rail analog inputs for gains > 1 Simultaneous 50 Hz/60 Hz rejection at 25 SPS (single cycle settling) Diagnostic functions (which aid safe integrity level (SIL) certification Crosspoint multiplexed analog inputs 4 differential/7 pseudo differential inputs Programmable gain (1 to 128) Band gap reference with 10 ppm/°C drift maximum (70 μA) Matched programmable excitation currents Internal clock oscillator On-chip bias voltage generator Low-side power switch General-purpose outputs Multiple filter options Internal temperature sensor Self and system calibration Sensor burnout detection Automatic channel sequencer Per channel configuration Power supply: 2.7 V to 3.6 V and ±1.8 V Independent interface power supply Power-down current: 5 μA maximum Temperature range: −40°C to +125°C 32-lead LFCSP/24-lead TSSOP 3-wire or 4-wire serial interface SPI, QSPI, MICROWIRE, and DSP compatible Schmitt trigger on SCLK ESD: 4 kVAD7124-4-EP Supports defense and aerospace applications (AQEC standard) Download AD7124-4-EP Data Sheet (PDF) Full military temperature range: −55°C to +125°C Controlled manufacturing baseline 1 assembly/test site 1 fabrication site Product change notification Qualification data available on request V62/19614

4-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference Features: Three power modes RMS noise Low power: 24 nV rms at 1.17 SPS, gain = 128 (255 μA typical) Mid power: 20 nV rms at 2.34 SPS, gain = 128 (355 μA typical) Full power: 23 nV rms at 9.4 SPS, gain = 128 (930 μA typical) Up to 22 noise free bits in all power modes (gain = 1) Output data rate Full power: 9.38 SPS to 19,200 SPS Mid power: 2.34 SPS to 4800 SPS Low power: 1.17 SPS to 2400 SPS Rail-to-rail analog inputs for gains > 1 Simultaneous 50 Hz/60 Hz rejection at 25 SPS (single cycle settling) Diagnostic functions (which aid safe integrity level (SIL) certification Crosspoint multiplexed analog inputs 4 differential/7 pseudo differential inputs Programmable gain (1 to 128) Band gap reference with 10 ppm/°C drift maximum (70 μA) Matched programmable excitation currents Internal clock oscillator On-chip bias voltage generator Low-side power switch General-purpose outputs Multiple filter options Internal temperature sensor Self and system calibration Sensor burnout detection Automatic channel sequencer Per channel configuration Power supply: 2.7 V to 3.6 V and ±1.8 V Independent interface power supply Power-down current: 5 μA maximum Temperature range: −40°C to +125°C 32-lead LFCSP/24-lead TSSOP 3-wire or 4-wire serial interface SPI, QSPI, MICROWIRE, and DSP compatible Schmitt trigger on SCLK ESD: 4 kVAD7124-4-EP Supports defense and aerospace applications (AQEC standard) Download AD7124-4-EP Data Sheet (PDF) Full military temperature range: −55°C to +125°C Controlled manufacturing baseline 1 assembly/test site 1 fabrication site Product change notification Qualification data available on request V62/19614

4-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference Features: Three power modes RMS noise Low power: 24 nV rms at 1.17 SPS, gain = 128 (255 μA typical) Mid power: 20 nV rms at 2.34 SPS, gain = 128 (355 μA typical) Full power: 23 nV rms at 9.4 SPS, gain = 128 (930 μA typical) Up to 22 noise free bits in all power modes (gain = 1) Output data rate Full power: 9.38 SPS to 19,200 SPS Mid power: 2.34 SPS to 4800 SPS Low power: 1.17 SPS to 2400 SPS Rail-to-rail analog inputs for gains > 1 Simultaneous 50 Hz/60 Hz rejection at 25 SPS (single cycle settling) Diagnostic functions (which aid safe integrity level (SIL) certification Crosspoint multiplexed analog inputs 4 differential/7 pseudo differential inputs Programmable gain (1 to 128) Band gap reference with 10 ppm/°C drift maximum (70 μA) Matched programmable excitation currents Internal clock oscillator On-chip bias voltage generator Low-side power switch General-purpose outputs Multiple filter options Internal temperature sensor Self and system calibration Sensor burnout detection Automatic channel sequencer Per channel configuration Power supply: 2.7 V to 3.6 V and ±1.8 V Independent interface power supply Power-down current: 5 μA maximum Temperature range: −40°C to +125°C 32-lead LFCSP/24-lead TSSOP 3-wire or 4-wire serial interface SPI, QSPI, MICROWIRE, and DSP compatible Schmitt trigger on SCLK ESD: 4 kVAD7124-4-EP Supports defense and aerospace applications (AQEC standard) Download AD7124-4-EP Data Sheet (PDF) Full military temperature range: −55°C to +125°C Controlled manufacturing baseline 1 assembly/test site 1 fabrication site Product change notification Qualification data available on request V62/19614

Dual, 16-Bit nanoDAC with I2C Interface Features: Low power, smallest pin-compatible, dual nanoDACs AD5627R/AD5647R/AD5667R 12-/14-/16-bit On-chip 1.25 V/2.5 V, 5 ppm/°C reference AD5627/AD5667 12-/16-bit External reference only 3 mm × 3 mm LFCSP and 10-lead MSOP 2.7 V to 5.5 V power supply Guaranteed monotonic by design Power-on reset to zero scale Per channel power-down Hardware LDAC and CLR functions I2C-compatible serial interface supports standard (100 kHz), fast (400 kHz), and high speed (3.4 MHz) modes

16-Channel, 12-BitnanoDAC+ with 2 ppm/C VoltageReference Temperature Coefficient, SPI Interface Features: High performance High relative accuracy (INL): ±1 LSB maximum at 12 bits TUE: ±0.14% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.06% of FSR maximum Low drift, 2.5 V voltage reference temperature coefficient: 2 ppm/°C typical 40 mA short-circuit current Wide operating ranges −40°C to +125°C temperature range 2.7 V to 5.5 V power supply range Simplified implementation User selectable gain of 1 or 2 (GAIN pin) 1.8 V logic compatibility 50 MHz serial peripheral interface (SPI) with readback or daisy chain 28-lead, 4 mm × 4 mm, RoHS compliant LFCSP

16-Channel, 12-BitnanoDAC+ with 2 ppm/C VoltageReference Temperature Coefficient, SPI Interface Features: High performance High relative accuracy (INL): ±1 LSB maximum at 12 bits TUE: ±0.14% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.06% of FSR maximum Low drift, 2.5 V voltage reference temperature coefficient: 2 ppm/°C typical 40 mA short-circuit current Wide operating ranges −40°C to +125°C temperature range 2.7 V to 5.5 V power supply range Simplified implementation User selectable gain of 1 or 2 (GAIN pin) 1.8 V logic compatibility 50 MHz serial peripheral interface (SPI) with readback or daisy chain 28-lead, 4 mm × 4 mm, RoHS compliant LFCSP

Octal, 16-Bit nanoDAC+ with I2C Interface Features: High performance High relative accuracy (INL): ±3 LSB maximum at 16 bits Total unadjusted error (TUE): ±0.14% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.06% of FSR maximum Wide operating ranges −40°C to +125°C temperature range 2.7 V to 5.5 V power supply Easy implementation User selectable gain of 1 or 2 (GAIN pin/bit) 1.8 V logic compatibility I2C-compatible serial interface Robust 2 kV HBM and 1.5 kV FICDM ESD rating 20-lead TSSOP and LFCSP RoHS-compliant packages

Octal, 16-Bit nanoDAC+ with I2C Interface Features: High performance High relative accuracy (INL): ±3 LSB maximum at 16 bits Total unadjusted error (TUE): ±0.14% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.06% of FSR maximum Wide operating ranges −40°C to +125°C temperature range 2.7 V to 5.5 V power supply Easy implementation User selectable gain of 1 or 2 (GAIN pin/bit) 1.8 V logic compatibility I2C-compatible serial interface Robust 2 kV HBM and 1.5 kV FICDM ESD rating 20-lead TSSOP and LFCSP RoHS-compliant packages

Octal, 16-Bit nanoDAC+ with 2 ppm/C Reference, I2CInterface Features: High Performance High relative accuracy (INL): ±3 LSB maximum at 16 bits Total unadjusted error (TUE): ±0.14% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.06% of FSR maximum Low drift 2.5 V reference: 2 ppm/°C typical Wide Operating Ranges −40°C to +125°C temperature range 2.7 V to 5.5 V power supply Easy Implementation User selectable gain of 1 or 2 (GAIN pin/bit) 1.8 V logic compatibility 400 kHz I2C-compatible serial interface 20-lead, RoHS-compliant TSSOP and LFCSP

16-Channel, 12-/16-Bit nanoDAC+ with 2 ppm/C Voltage Reference TC, I2C Interface Features: High relative accuracy (INL): ±4 LSB maximum at 16 bits (AD5677R only) TUE: ±0.14% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.06% of FSR maximum Low drift, 2.5 V voltage reference TC: 2 ppm/°C typical 40 mA short-circuit current Wide operating ranges −40°C to +125°C temperature range 2.7 V to 5.5 V power supply range Simplified implementation User selectable gain of 1 or 2 (GAIN pin) 1.8 V logic compatibility 400 kHz I2C-compatible serial interface 28-lead, 4 mm × 4 mm, RoHS compliant LFCSP

16-Channel, 12-/16-Bit nanoDAC+ with 2 ppm/C VoltageReference Temperature Coefficient, SPI Interface Features: High performance High relative accuracy (INL): ±4 LSB maximum at 16 bits (AD5679/AD5679R) TUE: ±0.14% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.06% of FSR maximum Low drift, 2.5 V voltage reference temperature coefficient: 2 ppm/°C typical 40 mA short-circuit current Wide operating ranges −40°C to +125°C temperature range 2.7 V to 5.5 V power supply range Simplified implementation User selectable gain of 1 or 2 (GAIN pin) 1.8 V logic compatibility 50 MHz serial peripheral interface (SPI) with readback or daisy chain 28-lead, 4 mm × 4 mm, RoHS compliant LFCSP

Dual, 12-BitnanoDAC+ with 2 ppm/C Reference, SPI Interface Features: High relative accuracy (INL): ±2 LSB maximum at 16 bits  Low drift 2.5 V reference: 2 ppm/°C typical Tiny package: 3 mm × 3 mm, 16-lead LFCSP TUE: ±0.1% of FSR maximum  Offset error: ±1.5 mV maximum Gain error: ±0.1% of FSR maximum High drive capability: 20 mA, 0.5 V from supply rails  User-selectable gain of 1 or 2 (GAIN pin)  Reset to zero scale or midscale (RSTSEL pin) 1.8 V logic compatibility 50 MHz SPI with readback or daisy chain Low glitch: 0.5 nV-sec Low power: 3.3 mW at 3 V  2.7 V to 5.5 V power supply −40°C to +105°C temperature range AEC-Q100 qualified for automotive applications