AD9215BRU-80EB
Part Number : AD9215BRU-80EB
Analog Devices Inc.High Speed ADC USB FIFO Evaluation Kit
AD9215BRU-105EB
Part Number : AD9215BRU-105EB
Analog Devices Inc.High Speed ADC USB FIFO Evaluation Kit
AD9216-105PCB
Part Number : AD9216-105PCB
Analog Devices Inc.High Speed ADC USB FIFO Evaluation Kit
AD9248BCP-40EB
Part Number : AD9248BCP-40EB
Analog Devices Inc.High Speed ADC USB FIFO Evaluation Kit
AD9287-100EB1
Part Number : AD9287-100EB1
Analog Devices Inc.High Speed ADC USB FIFO Evaluation Kit
AD9460-105EB-BB
Part Number : AD9460-105EB-BB
Analog Devices Inc.High Speed ADC USB FIFO Evaluation Kit
AD9480-LVDS/PCB2
Part Number : AD9480-LVDS/PCB2
Analog Devices Inc.High Speed ADC USB FIFO Evaluation Kit
ADP3650
Part Number : ADP3650
Analog Devices Inc.Dual, Bootstrapped, 12 V MOSFET Driver with Output Disable
AD9231
Part Number : AD9231
Analog Devices Inc.12-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter
AD9231BCPZRL7-65
Part Number : AD9231BCPZRL7-65
Analog Devices Inc.12-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter Features: 1.8 V analog supply operation 1.8 V to 3.3 V output supply SNR 71.3 dBFS at 9.7 MHz input 69.0 dBFS at 200 MHz input SFDR 93 dBc at 9.7 MHz input 83 dBc at 200 MHz input Low power 32 mW per channel at 20 MSPS 71 mW per channel at 80 MSPS Differential input with 700 MHz bandwidth 2 V p-p differential analog input On-chip voltage reference and sample-and-hold circuit DNL = ±0.40 LSB Serial port control options Offset binary, gray code, or twos complement data format Optional clock duty cycle stabilizer Integer 1-to-8 input clock divider Data output multiplex option Built-in selectable digital test pattern generation Energy-saving power-down modes Data clock out with programmable clock and data alignment
AD9231-20EBZ
Part Number : AD9231-20EBZ
Analog Devices Inc.12-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter Features: 1.8 V analog supply operation 1.8 V to 3.3 V output supply SNR 71.3 dBFS at 9.7 MHz input 69.0 dBFS at 200 MHz input SFDR 93 dBc at 9.7 MHz input 83 dBc at 200 MHz input Low power 32 mW per channel at 20 MSPS 71 mW per channel at 80 MSPS Differential input with 700 MHz bandwidth 2 V p-p differential analog input On-chip voltage reference and sample-and-hold circuit DNL = ±0.40 LSB Serial port control options Offset binary, gray code, or twos complement data format Optional clock duty cycle stabilizer Integer 1-to-8 input clock divider Data output multiplex option Built-in selectable digital test pattern generation Energy-saving power-down modes Data clock out with programmable clock and data alignment
