FPGA Zynq UltraScale+ 154350 Cells 20nm Technology 0.85V 484-Pin FCBGA Tray

The Initiator/Target core for PCI is a pre-implemented and fully tested module for Xilinx FPGAs. The pinout for each device and the relative placement of the internal logic are predefined.

REED SOLOMON ENCODER IMPLEMENTS MANY DIFFERENT REED SOLOMON CODING STANDARDSThe Reed-Solomon Encoder LogiCORE module is a high speedand compact design that implements many different Reed-Solomon coding.

DEVELOPMENT SYSTEM

LOGICORE, INTERLEAVER/DE-INTERLEAVER, SITE LICENSE RENEWAL

LOGICORE, REED SOLOMON DECODER, SITE LICENSE RENEWAL

The Xilinx CAN IP core is ideally suited for automotive and industrial applications such as automotive gatewaysand body control unitsand automotive test equipmentand instrument clustersand sensor controlsand and industrial networks.

The 3GPP LTE Channel Decoder provides a high-performanceand optimized decode function for the Uplink Shared Channel (UL-SCH)and as defined in 3GPP TS 26.212 v9.3.0.

The 3GPP LTE Channel Encoder performs the 'outer' transmit functions for the Physical Downlink Shared (PDSCH)and Multicast (PMCH)and Paging (PPCH)and Control (PDCCH) and Broadcast (PBCH) channels.

Logicore IP Is A High-Performance, Low Cost Flexible Solution

The Interleaver/De-interleaver LogiCORE module is a high-speedand compact design that is fully synchronousand using a single clock. It's parameterizable features support both the Forney Convolutional architecture and the Rectangular Block architecture.

License For Tri-Mode Ethernet Media Access Controller

FPGA SPARTAN-6 LX 3K 144TQFP; No. of Logic Blocks:600; No. of Macrocells:3840; FPGA Family:Spartan-6; Logic Case Style:QFP; No. of Pins:144Pins; No. of Speed Grades:2; Total RAM Bits:221184; No. of I/O's:102I/O's; Clock ;RoHS Compliant: Yes

XCKU5P Kintex UltraScale+ FPGA Evaluation Kit

FPGA Zynq-7000 Family 125000 Cells 200MHz 28nm Technology 2.5V 485-Pin FCBGA Tray

CMOS ISP CPLD 9572 TQFP100 3.3V; CPLD Type:FLASH; No. of Macrocells:72; No. of I/O's:72I/O's; Logic Case Style:TQFP; No. of Pins:100Pins; Frequency:100MHz; Supply Voltage Min:3V; Supply Voltage Max:3.6V; Propagation Delay:10ns; Global Clock Setup Time:6.5ns; Operating Temperature Min:0°C; Operating Temperature Max:70°C; Packaging:Peel Pack; Product Range:XC9500XL Series; MSL:MSL 3 - 168 hours; Base Number:9572; IC Generic Number:9572; IC Temperature Range:Commercial; Logic Function Number:9572; Logic IC Base Number:9572; Logic IC Function:Programmable ISP; No. of Gates:1600; Operating Temperature Range:0°C to +70°C; Programmable Logic Type:CPLD; Supply Voltage:3.3V; Supply Voltage Range:3V to 3.6V; Termination Type:Surface Mount Device

FPGA - Field Programmable Gate Array 30816 Logic Cells 12 Rocket IOs 2 Power PC 405

FPGA XC7S75 Family 48000 Logic Units 76800 Cells 464.25MHz 1V 676-Pin WBFPBGA Tray

XCVE1752-1LLINSVG1369

XILINX ZYNQ ULTRASCALE+ RFSOC DFE ZCU670 EVALUATION KIT