Wideband Receiver Design Using 66AK2L06 JESD204B Attach to ADC32RF80 Reference Design
Description
For wideband receiver system developers currently using FPGA or ASIC to connect High Speed data converters to a baseband processor: who need faster time to market with increased performance and significant reduction in cost: power: and size. This reference design includes the first widely available processor integrating a JESD204B interface and Digital Front End Processing (DFE). Connecting ADC32RF80 to DAC38J84 provides an efficient solution for avionics and defense: test and measurements and industrial applications.
Features
- Easy integration of signal processor to data converters over JESD204BUsable bandwidth of two 75MHz channels or a single 100MHz channel when connected to ADC32RF80DFE processing for filtering: down-sampling or up-sampling: FFTC hardware accelerator to offload comput-intensive 2D FFT operation: achieving low latency and high accuracyWideband sampling with JESD attached signal processing solution including Digital Signal Processor (DSP): ADC and DAC boards: demo software: configuration GUIs and getting started guideA robust demonstration and development platform including three EVMs: a deterministic latency card: schematic: BOM: user guide: benchmarks: software and demos
Applications
- Oscilloscopes & digitizers
- Small cell base station
- Software defined radio
- Spectrum analyzer
- Electronic warfare
- Seeker front end
- Global positioning system receiver
- Outdoor backhaul unit
- Radar
- Vector signal transceiver (VST)
- Indoor backhaul
- Wireless communications test