Optimized Radar System Reference Design Using a DSP+ARM SoC
Description
For modern radar system developers currently using an FPGA or ASIC to connect to high speed data converters: who need faster time to market with increased performance and significant reduction in cost: power: and size: this reference design includes the first widely available processor integrating a JESD204B interface and Digital Front End (DFE) processing. Connecting to the ADC14X250 and DAC38J84 provides an efficient solution for avionics and defense applications such radar: electronic warfare: compute platforms and transponders.
Features
- Easy integration of signal processor to data converters over JESD204BSampling of a single 100MHz channel: when connected to ADC14X250DFE processing for filtering: down-sampling or up-sampling; FFTC hardware accelerator to offload compute-intensive 2D FFT operations: achieving low latency and high accuracyWideband sampling with JESD attached signal processing solution including Digital Signal Processor (DSP): ADC and DAC boards: demo software: configuration GUIs and Getting Started GuideA robust demonstration and development platform including three EVMs: a deterministic latency card: schematic: BOM: user guide: benchmarks: software and demos
Applications
- Oscilloscopes & digitizers
- ATMs (Automated Teller Machines)
- Spectrum analyzer
- Electronic warfare
- Seeker front end
- Radar
- Vector signal transceiver (VST)
- Mother & neonatal care monitor
- Surgical equipment
- Robot sensor module
- Mobile robot sensor
- Motorized electronic wheel chair
- Medical chair & table
- Ultrasound smart probe
- Ultrasound scanner
- Wireless communications test
- Operation tables
- Dental chairs
Product Categories
| Title | Updated | Type | Size (KB) |
|---|---|---|---|
| 66AK2L06 JESD Attachment to ADC14X250/DAC38J84 | 10 Dec 2015 | 3670 |
| Download the bill of materials for TIDEP0060 | Download |
Test Data
Get results faster with test and simulation data that's been verified.
Download the test file for TIDEP0060| Title | Updated | Type | Size (KB) | |
|---|---|---|---|---|
| Optimized Radar System Using a DSP+ARM SoC Design Package (ADC14X250) | 04 Feb 2016 | ZIP | 4391 | |
| Optimized Radar System Using a DSP+ARM SoC Design Package (Adapter Card) | 04 Feb 2016 | ZIP | 2281 | |
| Optimized Radar System Using a DSP+ARM SoC Design Package BOM | 04 Feb 2016 | 100 | ||
| Optimized Radar System Using a DSP+ARM SoC Design Package Schematic | 04 Feb 2016 | 1357 |