Generating AVS SmartReflex Core Voltage for K2E Using TPS544C25 and PMBus Reference Design
Description
The K2E requires the use of AVS SmartReflex control for the CVDD core voltage. This design provides method of generating the proper voltage using software and the PMBus interface of the TPS544C25. The circuit can be implemented on the XEVMK2EX.
Features
- Provides the AVS SmartReflex Core voltage required by the K2EMeets the 5% voltage requirement for CVDDUses the PMBus interface on the TPS544C25 for controlUses software to send the VOUT commandComplete system reference with schematics: BOM: design files: and HW Design Guide: implemented on the K2E EVM platform for testing and evaluation
Applications
- Multifunction relay
Product Categories
| Application Area | End Equipment |
|---|---|
| Multifunction relay | https://www.ti.com/solution/multi-function-relay#referencedesigns |
| Download the bill of materials for TIDEP0042 | Download |
Test Data
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Download the test file for TIDEP0042| Title | Updated | Type | Size (KB) | |
|---|---|---|---|---|
| Generating AVS SMartReflex Core Voltage Schematic and Block Diagram | 09 Sep 2015 | 469 | ||
| Generating AVS SmartReflex Core Voltage for K2E BOM | 02 Jul 2015 | 67 | ||
| K2E Clock Generation Reference Design Layer Plots (PCBs) | 08 Oct 2014 | ZIP | 7495 | |
| K2E Clock Generation Reference Design Gerber | 08 Oct 2014 | ZIP | 26925 |