SPI Master with Signal Path Delay Compensation Reference Design
Description
The Programmable Real-time Unit within the Industrial Communication Subsystem (PRU-ICSS) enables you to support real-time critical applications without using FPGAs: CPLDs or ASICs.This reference design describes the implementation of the SPI master protocol with signal path delay compensation on PRU-ICSS. It supports the 32-bit communication protocol of ADS8688 with a SPI clock frequency of up to 16.7 MHz.
Features
- SPI master protocol with adjustable signal path delay compensation (not requiring external hardware for signal path delay compensation)Up to 16.7-MHz SPI clockSupports ADS8688 SPI-communication protocolAutomatic measurement of signal path delay for known secondary responseThis PRU-ICSS firmware has been validated with TIDA-00164 (ADS8688 and ISO7141CC) and contains firmware source code: implementation description and getting started instructions.
Applications
- Analog input module
- Desktop POS
- ATMs (Automated Teller Machines)
- Single board computer
- Mixed module (AI
- AO
- DI
- DO)
- Robot I/O module
- Computer on module
- Condition monitoring module
- Machine to machine
- Substation automation
Product Categories
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| Download the bill of materials for TIDEP0033 | Download |
| Title | Updated | Type | Size (KB) | |
|---|---|---|---|---|
| SPI Master With Signal Path Delay Compensation on PRU-ICSS Gerber | 15 Jun 2015 | ZIP | 5563 | |
| SPI Master With Signal Path Delay Compensation on PRU-ICSS CAD Files | 15 Jun 2015 | ZIP | 384 | |
| SPI Master With Signal Path Delay Compensation on PRU-ICSS PCB | 15 Jun 2015 | ZIP | 447 | |
| SPI Master With Signal Path Delay Compensation on PRU-ICSS Assembly Drawing | 15 Jun 2015 | ZIP | 447 | |
| SPI Master With Signal Path Delay Compensation on PRU-ICSS BOM | 15 Jun 2015 | 124 | ||
| SPI Master With Signal Path Delay Compensation on PRU-ICSS Schematic | 15 Jun 2015 | 248 |