PRU Real-Time I/O Evaluation Reference Design
Description
This reference design is a BeagleBone Black add-on board that allows users get to know TI’s powerful Programmable Real-Time Unit (PRU) core and basic functionality. The PRU is a low-latency microcontroller subsystem integrated in the Sitara AM335x and AM437x family of devices. The PRU core is optimized for deterministic: real-time processing: direct access to I/Os and ultra-low-latency requirements. With LEDs and push buttons for GPIO: audio: a temp sensor: optional character display and more: this add-on board includes schematics: bill of materials (BOM): design files: and design guide to teach the basics of the PRU.
Features
- PRU low-latency microcontroller subsystem integrated in Sitara Cortex-A8 based AM335x processor32-Bit RISC architecture: 200 MHz (5 ns) per instruction: single cycle execution: dedicated instruction and data RAM: additional shared RAM: 200 MHz ( 5ns) I/O interfaceBeagleBone Black compatible add-on board includes push buttons: I/O header: basic audio: UART (DB9): HDQ temperature sensor: proto board area: optional 8x2 LCD character displayComplete set of reference materials including schematics: BOM: board design files: and design guide
Applications
- Barcode scanner
- Oscilloscopes & digitizers
- Currency counter
- Digital multimeter (DMM)
- Portable data terminal
- Spectrometer
- Portable POS
- Lab & field Instrumentation
- Automotive test
- POS printer
- Source measurement unit (SMU)
- Weigh scale
Product Categories
| Download the bill of materials for TIDEP0017 | Download |
| Title | Updated | Type | Size (KB) | |
|---|---|---|---|---|
| PRU Real-Time I/O Evaluation Reference Design CAD Files | 29 Jul 2014 | ZIP | 79 | |
| PRU Real-Time I/O Evaluation Reference Design Assembly Drawings | 29 Jul 2014 | ZIP | 153 | |
| PRU Real-Time I/O Evaluation Reference Design PCB Layouts | 29 Jul 2014 | ZIP | 1620 | |
| PRU Real-Time I/O Evaluation Reference Design Bill of Materials (BOM) | 29 Jul 2014 | ZIP | 24 | |
| PRU Real-Time I/O Evaluation Reference Design Schematic | 28 Jul 2014 | 53 |