High Channel Count JESD204B Clock Generation Reference Design for RADAR and 5G Wireless Testers
Description
High-speed multi-channel applications require low noise and scalable clocking solutions capable of precise channel-to-channel skew adjustment to achieve optimal system SNR: SFDR: and ENOB. This reference design supports high channel count JESD204B synchronized clocks using one master and multiple slave clocking devices. This design provides multichannel JESD204B clocks using TI’s LMK04828 clock jitter cleaner and LMX2594 wideband PLL with integrated VCOs to achieve clock-to-clock skew of <10 ps. This design is tested with TI’s ADC12DJ3200 EVMs at 3 GSPS: and a channel-to-channel skew of < 50 ps is achieved with improved SNR performance. All key design theories are described to guide users through the part selection process and design optimization. Finally: schematics: board layouts: hardware testing: and test results are included.
Features
- High frequency (GSPS) sample clock generationHigh channel count and scalable JESD204B compliant clock solutionLow phase noise clocking for RF sampling ADC/DACConfigurable phase synchronization to achieve low skew in multi-channel systemSupports TI’s high-speed converter and capture cards (ADC12DJ3200EVM: TSW14J56 / TSW14J57)
Applications
- Oscilloscopes & digitizers
- Small cell base station
- Electronic warfare
- Outdoor backhaul unit
- Active antenna system mMIMO (AAS)
- Radar
- Signal generator
- Drone vision
- Indoor backhaul
- Macro remote radio unit (RRU)
- Ultrasound scanner
- Wireless communications test
Product Categories
- Data converters